Lines Matching +full:uniphier +full:- +full:uart
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier sLD8 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
11 compatible = "socionext,uniphier-sld8";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a9";
23 enable-method = "psci";
24 next-level-cache = <&l2>;
29 compatible = "arm,psci-0.2";
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <25000000>;
40 arm_timer_clk: arm-timer {
41 #clock-cells = <0>;
42 compatible = "fixed-clock";
43 clock-frequency = <50000000>;
48 compatible = "simple-bus";
49 #address-cells = <1>;
50 #size-cells = <1>;
52 interrupt-parent = <&intc>;
54 l2: cache-controller@500c0000 {
55 compatible = "socionext,uniphier-system-cache";
59 cache-unified;
60 cache-size = <(256 * 1024)>;
61 cache-sets = <256>;
62 cache-line-size = <128>;
63 cache-level = <2>;
67 compatible = "socionext,uniphier-scssi";
70 #address-cells = <1>;
71 #size-cells = <0>;
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_spi0>;
80 compatible = "socionext,uniphier-uart";
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_uart0>;
91 compatible = "socionext,uniphier-uart";
95 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_uart1>;
102 compatible = "socionext,uniphier-uart";
106 pinctrl-names = "default";
107 pinctrl-0 = <&pinctrl_uart2>;
113 compatible = "socionext,uniphier-uart";
117 pinctrl-names = "default";
118 pinctrl-0 = <&pinctrl_uart3>;
124 compatible = "socionext,uniphier-gpio";
126 interrupt-parent = <&aidet>;
127 interrupt-controller;
128 #interrupt-cells = <2>;
129 gpio-controller;
130 #gpio-cells = <2>;
131 gpio-ranges = <&pinctrl 0 0 0>,
134 gpio-ranges-group-names = "gpio_range0",
138 socionext,interrupt-ranges = <0 48 13>, <14 62 2>;
142 compatible = "socionext,uniphier-i2c";
145 #address-cells = <1>;
146 #size-cells = <0>;
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_i2c0>;
152 clock-frequency = <100000>;
156 compatible = "socionext,uniphier-i2c";
159 #address-cells = <1>;
160 #size-cells = <0>;
162 pinctrl-names = "default";
163 pinctrl-0 = <&pinctrl_i2c1>;
166 clock-frequency = <100000>;
169 /* chip-internal connection for DMD */
171 compatible = "socionext,uniphier-i2c";
173 #address-cells = <1>;
174 #size-cells = <0>;
176 pinctrl-names = "default";
177 pinctrl-0 = <&pinctrl_i2c2>;
180 clock-frequency = <400000>;
184 compatible = "socionext,uniphier-i2c";
187 #address-cells = <1>;
188 #size-cells = <0>;
190 pinctrl-names = "default";
191 pinctrl-0 = <&pinctrl_i2c3>;
194 clock-frequency = <100000>;
197 system_bus: system-bus@58c00000 {
198 compatible = "socionext,uniphier-system-bus";
201 #address-cells = <2>;
202 #size-cells = <1>;
203 pinctrl-names = "default";
204 pinctrl-0 = <&pinctrl_system_bus>;
208 compatible = "socionext,uniphier-smpctrl";
213 compatible = "socionext,uniphier-sld8-mioctrl",
214 "simple-mfd", "syscon";
218 compatible = "socionext,uniphier-sld8-mio-clock";
219 #clock-cells = <1>;
223 compatible = "socionext,uniphier-sld8-mio-reset";
224 #reset-cells = <1>;
229 compatible = "socionext,uniphier-sld8-perictrl",
230 "simple-mfd", "syscon";
234 compatible = "socionext,uniphier-sld8-peri-clock";
235 #clock-cells = <1>;
239 compatible = "socionext,uniphier-sld8-peri-reset";
240 #reset-cells = <1>;
244 dmac: dma-controller@5a000000 {
245 compatible = "socionext,uniphier-mio-dmac";
251 #dma-cells = <1>;
255 compatible = "socionext,uniphier-sd-v2.91";
259 pinctrl-names = "default", "uhs";
260 pinctrl-0 = <&pinctrl_sd>;
261 pinctrl-1 = <&pinctrl_sd_uhs>;
263 reset-names = "host", "bridge";
265 dma-names = "rx-tx";
267 bus-width = <4>;
268 cap-sd-highspeed;
269 sd-uhs-sdr12;
270 sd-uhs-sdr25;
271 sd-uhs-sdr50;
275 compatible = "socionext,uniphier-sd-v2.91";
279 pinctrl-names = "default";
280 pinctrl-0 = <&pinctrl_emmc>;
282 reset-names = "host", "bridge", "hw";
284 dma-names = "rx-tx";
286 bus-width = <8>;
287 cap-mmc-highspeed;
288 cap-mmc-hw-reset;
289 non-removable;
293 compatible = "socionext,uniphier-ehci", "generic-ehci";
297 pinctrl-names = "default";
298 pinctrl-0 = <&pinctrl_usb0>;
303 has-transaction-translator;
307 compatible = "socionext,uniphier-ehci", "generic-ehci";
311 pinctrl-names = "default";
312 pinctrl-0 = <&pinctrl_usb1>;
317 has-transaction-translator;
321 compatible = "socionext,uniphier-ehci", "generic-ehci";
325 pinctrl-names = "default";
326 pinctrl-0 = <&pinctrl_usb2>;
331 has-transaction-translator;
334 soc-glue@5f800000 {
335 compatible = "socionext,uniphier-sld8-soc-glue",
336 "simple-mfd", "syscon";
340 compatible = "socionext,uniphier-sld8-pinctrl";
344 soc-glue@5f900000 {
345 compatible = "socionext,uniphier-sld8-soc-glue-debug",
346 "simple-mfd";
347 #address-cells = <1>;
348 #size-cells = <1>;
352 compatible = "socionext,uniphier-efuse";
357 compatible = "socionext,uniphier-efuse";
363 compatible = "arm,cortex-a9-global-timer";
370 compatible = "arm,cortex-a9-twd-timer";
376 intc: interrupt-controller@60001000 {
377 compatible = "arm,cortex-a9-gic";
380 #interrupt-cells = <3>;
381 interrupt-controller;
384 aidet: interrupt-controller@61830000 {
385 compatible = "socionext,uniphier-sld8-aidet";
387 interrupt-controller;
388 #interrupt-cells = <2>;
392 compatible = "socionext,uniphier-sld8-sysctrl",
393 "simple-mfd", "syscon";
397 compatible = "socionext,uniphier-sld8-clock";
398 #clock-cells = <1>;
402 compatible = "socionext,uniphier-sld8-reset";
403 #reset-cells = <1>;
407 nand: nand-controller@68000000 {
408 compatible = "socionext,uniphier-denali-nand-v5a";
410 reg-names = "nand_data", "denali_reg";
412 #address-cells = <1>;
413 #size-cells = <0>;
415 pinctrl-names = "default";
416 pinctrl-0 = <&pinctrl_nand>;
417 clock-names = "nand", "nand_x", "ecc";
419 reset-names = "nand", "reg";
425 #include "uniphier-pinctrl.dtsi"