Lines Matching +full:uniphier +full:- +full:uart
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier PXs2 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/thermal/thermal.h>
12 compatible = "socionext,uniphier-pxs2";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a9";
25 enable-method = "psci";
26 next-level-cache = <&l2>;
27 operating-points-v2 = <&cpu_opp>;
28 #cooling-cells = <2>;
33 compatible = "arm,cortex-a9";
36 enable-method = "psci";
37 next-level-cache = <&l2>;
38 operating-points-v2 = <&cpu_opp>;
39 #cooling-cells = <2>;
44 compatible = "arm,cortex-a9";
47 enable-method = "psci";
48 next-level-cache = <&l2>;
49 operating-points-v2 = <&cpu_opp>;
50 #cooling-cells = <2>;
55 compatible = "arm,cortex-a9";
58 enable-method = "psci";
59 next-level-cache = <&l2>;
60 operating-points-v2 = <&cpu_opp>;
61 #cooling-cells = <2>;
65 cpu_opp: opp-table {
66 compatible = "operating-points-v2";
67 opp-shared;
69 opp-100000000 {
70 opp-hz = /bits/ 64 <100000000>;
71 clock-latency-ns = <300>;
73 opp-150000000 {
74 opp-hz = /bits/ 64 <150000000>;
75 clock-latency-ns = <300>;
77 opp-200000000 {
78 opp-hz = /bits/ 64 <200000000>;
79 clock-latency-ns = <300>;
81 opp-300000000 {
82 opp-hz = /bits/ 64 <300000000>;
83 clock-latency-ns = <300>;
85 opp-400000000 {
86 opp-hz = /bits/ 64 <400000000>;
87 clock-latency-ns = <300>;
89 opp-600000000 {
90 opp-hz = /bits/ 64 <600000000>;
91 clock-latency-ns = <300>;
93 opp-800000000 {
94 opp-hz = /bits/ 64 <800000000>;
95 clock-latency-ns = <300>;
97 opp-1200000000 {
98 opp-hz = /bits/ 64 <1200000000>;
99 clock-latency-ns = <300>;
104 compatible = "arm,psci-0.2";
110 compatible = "fixed-clock";
111 #clock-cells = <0>;
112 clock-frequency = <25000000>;
115 arm_timer_clk: arm-timer {
116 #clock-cells = <0>;
117 compatible = "fixed-clock";
118 clock-frequency = <50000000>;
122 thermal-zones {
123 cpu-thermal {
124 polling-delay-passive = <250>; /* 250ms */
125 polling-delay = <1000>; /* 1000ms */
126 thermal-sensors = <&pvtctl>;
129 cpu_crit: cpu-crit {
134 cpu_alert: cpu-alert {
141 cooling-maps {
144 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
154 compatible = "simple-bus";
155 #address-cells = <1>;
156 #size-cells = <1>;
158 interrupt-parent = <&intc>;
160 l2: cache-controller@500c0000 {
161 compatible = "socionext,uniphier-system-cache";
165 cache-unified;
166 cache-size = <(1280 * 1024)>;
167 cache-sets = <512>;
168 cache-line-size = <128>;
169 cache-level = <2>;
173 compatible = "socionext,uniphier-scssi";
176 #address-cells = <1>;
177 #size-cells = <0>;
179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_spi0>;
186 compatible = "socionext,uniphier-scssi";
189 #address-cells = <1>;
190 #size-cells = <0>;
192 pinctrl-names = "default";
193 pinctrl-0 = <&pinctrl_spi1>;
199 compatible = "socionext,uniphier-uart";
203 pinctrl-names = "default";
204 pinctrl-0 = <&pinctrl_uart0>;
210 compatible = "socionext,uniphier-uart";
214 pinctrl-names = "default";
215 pinctrl-0 = <&pinctrl_uart1>;
221 compatible = "socionext,uniphier-uart";
225 pinctrl-names = "default";
226 pinctrl-0 = <&pinctrl_uart2>;
232 compatible = "socionext,uniphier-uart";
236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_uart3>;
243 compatible = "socionext,uniphier-gpio";
245 interrupt-parent = <&aidet>;
246 interrupt-controller;
247 #interrupt-cells = <2>;
248 gpio-controller;
249 #gpio-cells = <2>;
250 gpio-ranges = <&pinctrl 0 0 0>,
252 gpio-ranges-group-names = "gpio_range0",
255 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
260 compatible = "socionext,uniphier-pxs2-aio";
263 pinctrl-names = "default";
264 pinctrl-0 = <&pinctrl_ain1>,
271 clock-names = "aio";
273 reset-names = "aio";
275 #sound-dai-cells = <1>;
315 compatible = "socionext,uniphier-fi2c";
318 #address-cells = <1>;
319 #size-cells = <0>;
321 pinctrl-names = "default";
322 pinctrl-0 = <&pinctrl_i2c0>;
325 clock-frequency = <100000>;
329 compatible = "socionext,uniphier-fi2c";
332 #address-cells = <1>;
333 #size-cells = <0>;
335 pinctrl-names = "default";
336 pinctrl-0 = <&pinctrl_i2c1>;
339 clock-frequency = <100000>;
343 compatible = "socionext,uniphier-fi2c";
346 #address-cells = <1>;
347 #size-cells = <0>;
349 pinctrl-names = "default";
350 pinctrl-0 = <&pinctrl_i2c2>;
353 clock-frequency = <100000>;
357 compatible = "socionext,uniphier-fi2c";
360 #address-cells = <1>;
361 #size-cells = <0>;
363 pinctrl-names = "default";
364 pinctrl-0 = <&pinctrl_i2c3>;
367 clock-frequency = <100000>;
370 /* chip-internal connection for DMD */
372 compatible = "socionext,uniphier-fi2c";
374 #address-cells = <1>;
375 #size-cells = <0>;
379 clock-frequency = <400000>;
382 /* chip-internal connection for STM */
384 compatible = "socionext,uniphier-fi2c";
386 #address-cells = <1>;
387 #size-cells = <0>;
391 clock-frequency = <400000>;
394 /* chip-internal connection for HDMI */
396 compatible = "socionext,uniphier-fi2c";
398 #address-cells = <1>;
399 #size-cells = <0>;
403 clock-frequency = <400000>;
406 system_bus: system-bus@58c00000 {
407 compatible = "socionext,uniphier-system-bus";
410 #address-cells = <2>;
411 #size-cells = <1>;
412 pinctrl-names = "default";
413 pinctrl-0 = <&pinctrl_system_bus>;
417 compatible = "socionext,uniphier-smpctrl";
422 compatible = "socionext,uniphier-pxs2-sdctrl",
423 "simple-mfd", "syscon";
427 compatible = "socionext,uniphier-pxs2-sd-clock";
428 #clock-cells = <1>;
432 compatible = "socionext,uniphier-pxs2-sd-reset";
433 #reset-cells = <1>;
438 compatible = "socionext,uniphier-pxs2-perictrl",
439 "simple-mfd", "syscon";
443 compatible = "socionext,uniphier-pxs2-peri-clock";
444 #clock-cells = <1>;
448 compatible = "socionext,uniphier-pxs2-peri-reset";
449 #reset-cells = <1>;
454 compatible = "socionext,uniphier-sd-v3.1.1";
458 pinctrl-names = "default";
459 pinctrl-0 = <&pinctrl_emmc>;
461 reset-names = "host", "hw";
463 bus-width = <8>;
464 cap-mmc-highspeed;
465 cap-mmc-hw-reset;
466 non-removable;
470 compatible = "socionext,uniphier-sd-v3.1.1";
474 pinctrl-names = "default", "uhs";
475 pinctrl-0 = <&pinctrl_sd>;
476 pinctrl-1 = <&pinctrl_sd_uhs>;
478 reset-names = "host";
480 bus-width = <4>;
481 cap-sd-highspeed;
482 sd-uhs-sdr12;
483 sd-uhs-sdr25;
484 sd-uhs-sdr50;
487 soc_glue: soc-glue@5f800000 {
488 compatible = "socionext,uniphier-pxs2-soc-glue",
489 "simple-mfd", "syscon";
493 compatible = "socionext,uniphier-pxs2-pinctrl";
497 soc-glue@5f900000 {
498 compatible = "socionext,uniphier-pxs2-soc-glue-debug",
499 "simple-mfd";
500 #address-cells = <1>;
501 #size-cells = <1>;
505 compatible = "socionext,uniphier-efuse";
510 compatible = "socionext,uniphier-efuse";
515 xdmac: dma-controller@5fc10000 {
516 compatible = "socionext,uniphier-xdmac";
519 dma-channels = <16>;
520 #dma-cells = <2>;
523 aidet: interrupt-controller@5fc20000 {
524 compatible = "socionext,uniphier-pxs2-aidet";
526 interrupt-controller;
527 #interrupt-cells = <2>;
531 compatible = "arm,cortex-a9-global-timer";
538 compatible = "arm,cortex-a9-twd-timer";
544 intc: interrupt-controller@60001000 {
545 compatible = "arm,cortex-a9-gic";
548 #interrupt-cells = <3>;
549 interrupt-controller;
553 compatible = "socionext,uniphier-pxs2-sysctrl",
554 "simple-mfd", "syscon";
558 compatible = "socionext,uniphier-pxs2-clock";
559 #clock-cells = <1>;
563 compatible = "socionext,uniphier-pxs2-reset";
564 #reset-cells = <1>;
568 compatible = "socionext,uniphier-pxs2-thermal";
570 #thermal-sensor-cells = <0>;
571 socionext,tmod-calibration = <0x0f86 0x6844>;
576 compatible = "socionext,uniphier-pxs2-ave4";
580 pinctrl-names = "default";
581 pinctrl-0 = <&pinctrl_ether_rgmii>;
582 clock-names = "ether";
584 reset-names = "ether";
586 phy-mode = "rgmii";
587 local-mac-address = [00 00 00 00 00 00];
588 socionext,syscon-phy-mode = <&soc_glue 0>;
591 #address-cells = <1>;
592 #size-cells = <0>;
597 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
600 interrupt-names = "host", "peripheral";
602 pinctrl-names = "default";
603 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
604 clock-names = "ref", "bus_early", "suspend";
612 usb-glue@65b00000 {
613 compatible = "socionext,uniphier-pxs2-dwc3-glue",
614 "simple-mfd";
615 #address-cells = <1>;
616 #size-cells = <1>;
620 compatible = "socionext,uniphier-pxs2-usb3-reset";
622 #reset-cells = <1>;
623 clock-names = "link";
625 reset-names = "link";
630 compatible = "socionext,uniphier-pxs2-usb3-regulator";
632 clock-names = "link";
634 reset-names = "link";
639 compatible = "socionext,uniphier-pxs2-usb3-regulator";
641 clock-names = "link";
643 reset-names = "link";
647 usb0_hsphy0: hs-phy@200 {
648 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
650 #phy-cells = <0>;
651 clock-names = "link", "phy";
653 reset-names = "link", "phy";
655 vbus-supply = <&usb0_vbus0>;
658 usb0_hsphy1: hs-phy@210 {
659 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
661 #phy-cells = <0>;
662 clock-names = "link", "phy";
664 reset-names = "link", "phy";
666 vbus-supply = <&usb0_vbus1>;
669 usb0_ssphy0: ss-phy@300 {
670 compatible = "socionext,uniphier-pxs2-usb3-ssphy";
672 #phy-cells = <0>;
673 clock-names = "link", "phy";
675 reset-names = "link", "phy";
677 vbus-supply = <&usb0_vbus0>;
680 usb0_ssphy1: ss-phy@310 {
681 compatible = "socionext,uniphier-pxs2-usb3-ssphy";
683 #phy-cells = <0>;
684 clock-names = "link", "phy";
686 reset-names = "link", "phy";
688 vbus-supply = <&usb0_vbus1>;
693 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
696 interrupt-names = "host", "peripheral";
698 pinctrl-names = "default";
699 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
700 clock-names = "ref", "bus_early", "suspend";
707 usb-glue@65d00000 {
708 compatible = "socionext,uniphier-pxs2-dwc3-glue",
709 "simple-mfd";
710 #address-cells = <1>;
711 #size-cells = <1>;
715 compatible = "socionext,uniphier-pxs2-usb3-reset";
717 #reset-cells = <1>;
718 clock-names = "link";
720 reset-names = "link";
725 compatible = "socionext,uniphier-pxs2-usb3-regulator";
727 clock-names = "link";
729 reset-names = "link";
734 compatible = "socionext,uniphier-pxs2-usb3-regulator";
736 clock-names = "link";
738 reset-names = "link";
742 usb1_hsphy0: hs-phy@200 {
743 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
745 #phy-cells = <0>;
746 clock-names = "link", "phy";
748 reset-names = "link", "phy";
750 vbus-supply = <&usb1_vbus0>;
753 usb1_hsphy1: hs-phy@210 {
754 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
756 #phy-cells = <0>;
757 clock-names = "link", "phy";
759 reset-names = "link", "phy";
761 vbus-supply = <&usb1_vbus1>;
764 usb1_ssphy0: ss-phy@300 {
765 compatible = "socionext,uniphier-pxs2-usb3-ssphy";
767 #phy-cells = <0>;
768 clock-names = "link", "phy";
770 reset-names = "link", "phy";
772 vbus-supply = <&usb1_vbus0>;
776 nand: nand-controller@68000000 {
777 compatible = "socionext,uniphier-denali-nand-v5b";
779 reg-names = "nand_data", "denali_reg";
781 #address-cells = <1>;
782 #size-cells = <0>;
784 pinctrl-names = "default";
785 pinctrl-0 = <&pinctrl_nand>;
786 clock-names = "nand", "nand_x", "ecc";
788 reset-names = "nand", "reg";
794 #include "uniphier-pinctrl.dtsi"