Lines Matching +full:uniphier +full:- +full:uart
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier Pro5 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
9 compatible = "socionext,uniphier-pro5";
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a9";
22 enable-method = "psci";
23 next-level-cache = <&l2>;
24 operating-points-v2 = <&cpu_opp>;
29 compatible = "arm,cortex-a9";
32 enable-method = "psci";
33 next-level-cache = <&l2>;
34 operating-points-v2 = <&cpu_opp>;
38 cpu_opp: opp-table {
39 compatible = "operating-points-v2";
40 opp-shared;
42 opp-100000000 {
43 opp-hz = /bits/ 64 <100000000>;
44 clock-latency-ns = <300>;
46 opp-116667000 {
47 opp-hz = /bits/ 64 <116667000>;
48 clock-latency-ns = <300>;
50 opp-150000000 {
51 opp-hz = /bits/ 64 <150000000>;
52 clock-latency-ns = <300>;
54 opp-175000000 {
55 opp-hz = /bits/ 64 <175000000>;
56 clock-latency-ns = <300>;
58 opp-200000000 {
59 opp-hz = /bits/ 64 <200000000>;
60 clock-latency-ns = <300>;
62 opp-233334000 {
63 opp-hz = /bits/ 64 <233334000>;
64 clock-latency-ns = <300>;
66 opp-300000000 {
67 opp-hz = /bits/ 64 <300000000>;
68 clock-latency-ns = <300>;
70 opp-350000000 {
71 opp-hz = /bits/ 64 <350000000>;
72 clock-latency-ns = <300>;
74 opp-400000000 {
75 opp-hz = /bits/ 64 <400000000>;
76 clock-latency-ns = <300>;
78 opp-466667000 {
79 opp-hz = /bits/ 64 <466667000>;
80 clock-latency-ns = <300>;
82 opp-600000000 {
83 opp-hz = /bits/ 64 <600000000>;
84 clock-latency-ns = <300>;
86 opp-700000000 {
87 opp-hz = /bits/ 64 <700000000>;
88 clock-latency-ns = <300>;
90 opp-800000000 {
91 opp-hz = /bits/ 64 <800000000>;
92 clock-latency-ns = <300>;
94 opp-933334000 {
95 opp-hz = /bits/ 64 <933334000>;
96 clock-latency-ns = <300>;
98 opp-1200000000 {
99 opp-hz = /bits/ 64 <1200000000>;
100 clock-latency-ns = <300>;
102 opp-1400000000 {
103 opp-hz = /bits/ 64 <1400000000>;
104 clock-latency-ns = <300>;
109 compatible = "arm,psci-0.2";
115 compatible = "fixed-clock";
116 #clock-cells = <0>;
117 clock-frequency = <20000000>;
120 arm_timer_clk: arm-timer {
121 #clock-cells = <0>;
122 compatible = "fixed-clock";
123 clock-frequency = <50000000>;
128 compatible = "simple-bus";
129 #address-cells = <1>;
130 #size-cells = <1>;
132 interrupt-parent = <&intc>;
134 l2: cache-controller@500c0000 {
135 compatible = "socionext,uniphier-system-cache";
139 cache-unified;
140 cache-size = <(2 * 1024 * 1024)>;
141 cache-sets = <512>;
142 cache-line-size = <128>;
143 cache-level = <2>;
144 next-level-cache = <&l3>;
147 l3: cache-controller@500c8000 {
148 compatible = "socionext,uniphier-system-cache";
152 cache-unified;
153 cache-size = <(2 * 1024 * 1024)>;
154 cache-sets = <512>;
155 cache-line-size = <256>;
156 cache-level = <3>;
160 compatible = "socionext,uniphier-scssi";
163 #address-cells = <1>;
164 #size-cells = <0>;
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_spi0>;
173 compatible = "socionext,uniphier-scssi";
176 #address-cells = <1>;
177 #size-cells = <0>;
179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_spi1>;
186 compatible = "socionext,uniphier-uart";
190 pinctrl-names = "default";
191 pinctrl-0 = <&pinctrl_uart0>;
197 compatible = "socionext,uniphier-uart";
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_uart1>;
208 compatible = "socionext,uniphier-uart";
212 pinctrl-names = "default";
213 pinctrl-0 = <&pinctrl_uart2>;
219 compatible = "socionext,uniphier-uart";
223 pinctrl-names = "default";
224 pinctrl-0 = <&pinctrl_uart3>;
230 compatible = "socionext,uniphier-gpio";
232 interrupt-parent = <&aidet>;
233 interrupt-controller;
234 #interrupt-cells = <2>;
235 gpio-controller;
236 #gpio-cells = <2>;
237 gpio-ranges = <&pinctrl 0 0 0>;
238 gpio-ranges-group-names = "gpio_range";
240 socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
244 compatible = "socionext,uniphier-fi2c";
247 #address-cells = <1>;
248 #size-cells = <0>;
250 pinctrl-names = "default";
251 pinctrl-0 = <&pinctrl_i2c0>;
254 clock-frequency = <100000>;
258 compatible = "socionext,uniphier-fi2c";
261 #address-cells = <1>;
262 #size-cells = <0>;
264 pinctrl-names = "default";
265 pinctrl-0 = <&pinctrl_i2c1>;
268 clock-frequency = <100000>;
272 compatible = "socionext,uniphier-fi2c";
275 #address-cells = <1>;
276 #size-cells = <0>;
278 pinctrl-names = "default";
279 pinctrl-0 = <&pinctrl_i2c2>;
282 clock-frequency = <100000>;
286 compatible = "socionext,uniphier-fi2c";
289 #address-cells = <1>;
290 #size-cells = <0>;
292 pinctrl-names = "default";
293 pinctrl-0 = <&pinctrl_i2c3>;
296 clock-frequency = <100000>;
301 /* chip-internal connection for DMD */
303 compatible = "socionext,uniphier-fi2c";
305 #address-cells = <1>;
306 #size-cells = <0>;
310 clock-frequency = <400000>;
313 /* chip-internal connection for HDMI */
315 compatible = "socionext,uniphier-fi2c";
317 #address-cells = <1>;
318 #size-cells = <0>;
322 clock-frequency = <400000>;
325 system_bus: system-bus@58c00000 {
326 compatible = "socionext,uniphier-system-bus";
329 #address-cells = <2>;
330 #size-cells = <1>;
331 pinctrl-names = "default";
332 pinctrl-0 = <&pinctrl_system_bus>;
336 compatible = "socionext,uniphier-smpctrl";
341 compatible = "socionext,uniphier-pro5-sdctrl",
342 "simple-mfd", "syscon";
346 compatible = "socionext,uniphier-pro5-sd-clock";
347 #clock-cells = <1>;
351 compatible = "socionext,uniphier-pro5-sd-reset";
352 #reset-cells = <1>;
357 compatible = "socionext,uniphier-pro5-perictrl",
358 "simple-mfd", "syscon";
362 compatible = "socionext,uniphier-pro5-peri-clock";
363 #clock-cells = <1>;
367 compatible = "socionext,uniphier-pro5-peri-reset";
368 #reset-cells = <1>;
372 soc-glue@5f800000 {
373 compatible = "socionext,uniphier-pro5-soc-glue",
374 "simple-mfd", "syscon";
378 compatible = "socionext,uniphier-pro5-pinctrl";
382 soc-glue@5f900000 {
383 compatible = "socionext,uniphier-pro5-soc-glue-debug",
384 "simple-mfd";
385 #address-cells = <1>;
386 #size-cells = <1>;
390 compatible = "socionext,uniphier-efuse";
395 compatible = "socionext,uniphier-efuse";
400 compatible = "socionext,uniphier-efuse";
405 compatible = "socionext,uniphier-efuse";
410 compatible = "socionext,uniphier-efuse";
415 xdmac: dma-controller@5fc10000 {
416 compatible = "socionext,uniphier-xdmac";
419 dma-channels = <16>;
420 #dma-cells = <2>;
423 aidet: interrupt-controller@5fc20000 {
424 compatible = "socionext,uniphier-pro5-aidet";
426 interrupt-controller;
427 #interrupt-cells = <2>;
431 compatible = "arm,cortex-a9-global-timer";
438 compatible = "arm,cortex-a9-twd-timer";
444 intc: interrupt-controller@60001000 {
445 compatible = "arm,cortex-a9-gic";
448 #interrupt-cells = <3>;
449 interrupt-controller;
453 compatible = "socionext,uniphier-pro5-sysctrl",
454 "simple-mfd", "syscon";
458 compatible = "socionext,uniphier-pro5-clock";
459 #clock-cells = <1>;
463 compatible = "socionext,uniphier-pro5-reset";
464 #reset-cells = <1>;
469 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
472 interrupt-names = "host";
474 pinctrl-names = "default";
475 pinctrl-0 = <&pinctrl_usb0>;
476 clock-names = "ref", "bus_early", "suspend";
483 usb-glue@65b00000 {
484 compatible = "socionext,uniphier-pro5-dwc3-glue",
485 "simple-mfd";
486 #address-cells = <1>;
487 #size-cells = <1>;
491 compatible = "socionext,uniphier-pro5-usb3-reset";
493 #reset-cells = <1>;
494 clock-names = "gio", "link";
496 reset-names = "gio", "link";
501 compatible = "socionext,uniphier-pro5-usb3-regulator";
503 clock-names = "gio", "link";
505 reset-names = "gio", "link";
509 usb0_hsphy0: hs-phy@280 {
510 compatible = "socionext,uniphier-pro5-usb3-hsphy";
512 #phy-cells = <0>;
513 clock-names = "gio", "link";
515 reset-names = "gio", "link";
517 vbus-supply = <&usb0_vbus0>;
520 usb0_ssphy0: ss-phy@380 {
521 compatible = "socionext,uniphier-pro5-usb3-ssphy";
523 #phy-cells = <0>;
524 clock-names = "gio", "link";
526 reset-names = "gio", "link";
528 vbus-supply = <&usb0_vbus0>;
533 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
536 interrupt-names = "host";
538 pinctrl-names = "default";
539 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
540 clock-names = "ref", "bus_early", "suspend";
547 usb-glue@65d00000 {
548 compatible = "socionext,uniphier-pro5-dwc3-glue",
549 "simple-mfd";
550 #address-cells = <1>;
551 #size-cells = <1>;
555 compatible = "socionext,uniphier-pro5-usb3-reset";
557 #reset-cells = <1>;
558 clock-names = "gio", "link";
560 reset-names = "gio", "link";
565 compatible = "socionext,uniphier-pro5-usb3-regulator";
567 clock-names = "gio", "link";
569 reset-names = "gio", "link";
574 compatible = "socionext,uniphier-pro5-usb3-regulator";
576 clock-names = "gio", "link";
578 reset-names = "gio", "link";
582 usb1_hsphy0: hs-phy@280 {
583 compatible = "socionext,uniphier-pro5-usb3-hsphy";
585 #phy-cells = <0>;
586 clock-names = "gio", "link";
588 reset-names = "gio", "link";
590 vbus-supply = <&usb1_vbus0>;
593 usb1_hsphy1: hs-phy@290 {
594 compatible = "socionext,uniphier-pro5-usb3-hsphy";
596 #phy-cells = <0>;
597 clock-names = "gio", "link";
599 reset-names = "gio", "link";
601 vbus-supply = <&usb1_vbus1>;
604 usb1_ssphy0: ss-phy@380 {
605 compatible = "socionext,uniphier-pro5-usb3-ssphy";
607 #phy-cells = <0>;
608 clock-names = "gio", "link";
610 reset-names = "gio", "link";
612 vbus-supply = <&usb1_vbus0>;
616 pcie_ep: pcie-ep@66000000 {
617 compatible = "socionext,uniphier-pro5-pcie-ep",
618 "snps,dw-pcie-ep";
620 reg-names = "dbi", "dbi2", "link", "addr_space";
623 pinctrl-names = "default";
624 pinctrl-0 = <&pinctrl_pcie>;
625 clock-names = "gio", "link";
627 reset-names = "gio", "link";
629 num-ib-windows = <16>;
630 num-ob-windows = <16>;
631 num-lanes = <4>;
632 phy-names = "pcie-phy";
637 compatible = "socionext,uniphier-pro5-pcie-phy";
639 #phy-cells = <0>;
640 clock-names = "gio", "link";
642 reset-names = "gio", "link";
646 nand: nand-controller@68000000 {
647 compatible = "socionext,uniphier-denali-nand-v5b";
649 reg-names = "nand_data", "denali_reg";
651 #address-cells = <1>;
652 #size-cells = <0>;
654 pinctrl-names = "default";
655 pinctrl-0 = <&pinctrl_nand>;
656 clock-names = "nand", "nand_x", "ecc";
658 reset-names = "nand", "reg";
663 compatible = "socionext,uniphier-sd-v3.1";
667 pinctrl-names = "default";
668 pinctrl-0 = <&pinctrl_emmc>;
670 reset-names = "host", "hw";
672 bus-width = <8>;
673 cap-mmc-highspeed;
674 cap-mmc-hw-reset;
675 non-removable;
679 compatible = "socionext,uniphier-sd-v3.1";
683 pinctrl-names = "default", "uhs";
684 pinctrl-0 = <&pinctrl_sd>;
685 pinctrl-1 = <&pinctrl_sd_uhs>;
687 reset-names = "host";
689 bus-width = <4>;
690 cap-sd-highspeed;
691 sd-uhs-sdr12;
692 sd-uhs-sdr25;
693 sd-uhs-sdr50;
698 #include "uniphier-pinctrl.dtsi"