Lines Matching +full:0 +full:x54006800
15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
116 #clock-cells = <0>;
121 #clock-cells = <0>;
136 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
137 <0x506c0000 0x400>;
138 interrupts = <0 190 4>, <0 191 4>;
149 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
150 <0x506c8000 0x400>;
151 interrupts = <0 174 4>, <0 175 4>;
162 reg = <0x54006000 0x100>;
164 #size-cells = <0>;
165 interrupts = <0 39 4>;
167 pinctrl-0 = <&pinctrl_spi0>;
175 reg = <0x54006100 0x100>;
177 #size-cells = <0>;
178 interrupts = <0 216 4>;
180 pinctrl-0 = <&pinctrl_spi1>;
188 reg = <0x54006800 0x40>;
189 interrupts = <0 33 4>;
191 pinctrl-0 = <&pinctrl_uart0>;
192 clocks = <&peri_clk 0>;
193 resets = <&peri_rst 0>;
199 reg = <0x54006900 0x40>;
200 interrupts = <0 35 4>;
202 pinctrl-0 = <&pinctrl_uart1>;
210 reg = <0x54006a00 0x40>;
211 interrupts = <0 37 4>;
213 pinctrl-0 = <&pinctrl_uart2>;
221 reg = <0x54006b00 0x40>;
222 interrupts = <0 177 4>;
224 pinctrl-0 = <&pinctrl_uart3>;
231 reg = <0x55000000 0x200>;
237 gpio-ranges = <&pinctrl 0 0 0>;
240 socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
246 reg = <0x58780000 0x80>;
248 #size-cells = <0>;
249 interrupts = <0 41 4>;
251 pinctrl-0 = <&pinctrl_i2c0>;
260 reg = <0x58781000 0x80>;
262 #size-cells = <0>;
263 interrupts = <0 42 4>;
265 pinctrl-0 = <&pinctrl_i2c1>;
274 reg = <0x58782000 0x80>;
276 #size-cells = <0>;
277 interrupts = <0 43 4>;
279 pinctrl-0 = <&pinctrl_i2c2>;
288 reg = <0x58783000 0x80>;
290 #size-cells = <0>;
291 interrupts = <0 44 4>;
293 pinctrl-0 = <&pinctrl_i2c3>;
304 reg = <0x58785000 0x80>;
306 #size-cells = <0>;
307 interrupts = <0 25 4>;
316 reg = <0x58786000 0x80>;
318 #size-cells = <0>;
319 interrupts = <0 26 4>;
328 reg = <0x58c00000 0x400>;
332 pinctrl-0 = <&pinctrl_system_bus>;
337 reg = <0x59801000 0x400>;
343 reg = <0x59810000 0x400>;
359 reg = <0x59820000 0x200>;
375 reg = <0x5f800000 0x2000>;
387 ranges = <0 0x5f900000 0x2000>;
391 reg = <0x100 0x28>;
396 reg = <0x130 0x8>;
401 reg = <0x200 0x28>;
406 reg = <0x300 0x14>;
411 reg = <0x400 0x8>;
417 reg = <0x5fc10000 0x5300>;
418 interrupts = <0 188 4>;
425 reg = <0x5fc20000 0x200>;
432 reg = <0x60000200 0x20>;
433 interrupts = <1 11 0x304>;
439 reg = <0x60000600 0x20>;
440 interrupts = <1 13 0x304>;
446 reg = <0x60001000 0x1000>,
447 <0x60000100 0x100>;
455 reg = <0x61840000 0x10000>;
471 reg = <0x65a00000 0xcd00>;
473 interrupts = <0 134 4>;
475 pinctrl-0 = <&pinctrl_usb0>;
488 ranges = <0 0x65b00000 0x400>;
490 usb0_rst: reset@0 {
492 reg = <0x0 0x4>;
502 reg = <0x100 0x10>;
511 reg = <0x280 0x10>;
512 #phy-cells = <0>;
522 reg = <0x380 0x10>;
523 #phy-cells = <0>;
535 reg = <0x65c00000 0xcd00>;
537 interrupts = <0 137 4>;
539 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
552 ranges = <0 0x65d00000 0x400>;
554 usb1_rst: reset@0 {
556 reg = <0x0 0x4>;
566 reg = <0x100 0x10>;
575 reg = <0x110 0x10>;
584 reg = <0x280 0x10>;
585 #phy-cells = <0>;
595 reg = <0x290 0x10>;
596 #phy-cells = <0>;
606 reg = <0x380 0x10>;
607 #phy-cells = <0>;
621 reg = <0x66000000 0x1000>, <0x66001000 0x1000>,
622 <0x66010000 0x10000>, <0x67000000 0x400000>;
624 pinctrl-0 = <&pinctrl_pcie>;
638 reg = <0x66038000 0x4000>;
639 #phy-cells = <0>;
650 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
652 #size-cells = <0>;
653 interrupts = <0 65 4>;
655 pinctrl-0 = <&pinctrl_nand>;
665 reg = <0x68400000 0x800>;
666 interrupts = <0 78 4>;
668 pinctrl-0 = <&pinctrl_emmc>;
681 reg = <0x68800000 0x800>;
682 interrupts = <0 76 4>;
684 pinctrl-0 = <&pinctrl_sd>;
686 clocks = <&sd_clk 0>;
688 resets = <&sd_rst 0>;