Lines Matching +full:uniphier +full:- +full:uart
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD4 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
11 compatible = "socionext,uniphier-ld4";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a9";
23 enable-method = "psci";
24 next-level-cache = <&l2>;
29 compatible = "arm,psci-0.2";
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <24576000>;
40 arm_timer_clk: arm-timer {
41 #clock-cells = <0>;
42 compatible = "fixed-clock";
43 clock-frequency = <50000000>;
48 compatible = "simple-bus";
49 #address-cells = <1>;
50 #size-cells = <1>;
52 interrupt-parent = <&intc>;
54 l2: cache-controller@500c0000 {
55 compatible = "socionext,uniphier-system-cache";
59 cache-unified;
60 cache-size = <(512 * 1024)>;
61 cache-sets = <256>;
62 cache-line-size = <128>;
63 cache-level = <2>;
67 compatible = "socionext,uniphier-scssi";
70 #address-cells = <1>;
71 #size-cells = <0>;
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_spi0>;
80 compatible = "socionext,uniphier-uart";
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_uart0>;
91 compatible = "socionext,uniphier-uart";
95 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_uart1>;
102 compatible = "socionext,uniphier-uart";
106 pinctrl-names = "default";
107 pinctrl-0 = <&pinctrl_uart2>;
113 compatible = "socionext,uniphier-uart";
117 pinctrl-names = "default";
118 pinctrl-0 = <&pinctrl_uart3>;
124 compatible = "socionext,uniphier-gpio";
126 interrupt-parent = <&aidet>;
127 interrupt-controller;
128 #interrupt-cells = <2>;
129 gpio-controller;
130 #gpio-cells = <2>;
131 gpio-ranges = <&pinctrl 0 0 0>;
132 gpio-ranges-group-names = "gpio_range";
134 socionext,interrupt-ranges = <0 48 13>, <14 62 2>;
138 compatible = "socionext,uniphier-i2c";
141 #address-cells = <1>;
142 #size-cells = <0>;
144 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_i2c0>;
148 clock-frequency = <100000>;
152 compatible = "socionext,uniphier-i2c";
155 #address-cells = <1>;
156 #size-cells = <0>;
158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_i2c1>;
162 clock-frequency = <100000>;
165 /* chip-internal connection for DMD */
167 compatible = "socionext,uniphier-i2c";
169 #address-cells = <1>;
170 #size-cells = <0>;
172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_i2c2>;
176 clock-frequency = <400000>;
180 compatible = "socionext,uniphier-i2c";
183 #address-cells = <1>;
184 #size-cells = <0>;
186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_i2c3>;
190 clock-frequency = <100000>;
193 system_bus: system-bus@58c00000 {
194 compatible = "socionext,uniphier-system-bus";
197 #address-cells = <2>;
198 #size-cells = <1>;
199 pinctrl-names = "default";
200 pinctrl-0 = <&pinctrl_system_bus>;
204 compatible = "socionext,uniphier-smpctrl";
209 compatible = "socionext,uniphier-ld4-mioctrl",
210 "simple-mfd", "syscon";
214 compatible = "socionext,uniphier-ld4-mio-clock";
215 #clock-cells = <1>;
219 compatible = "socionext,uniphier-ld4-mio-reset";
220 #reset-cells = <1>;
225 compatible = "socionext,uniphier-ld4-perictrl",
226 "simple-mfd", "syscon";
230 compatible = "socionext,uniphier-ld4-peri-clock";
231 #clock-cells = <1>;
235 compatible = "socionext,uniphier-ld4-peri-reset";
236 #reset-cells = <1>;
240 dmac: dma-controller@5a000000 {
241 compatible = "socionext,uniphier-mio-dmac";
247 #dma-cells = <1>;
251 compatible = "socionext,uniphier-sd-v2.91";
255 pinctrl-names = "default", "uhs";
256 pinctrl-0 = <&pinctrl_sd>;
257 pinctrl-1 = <&pinctrl_sd_uhs>;
259 reset-names = "host", "bridge";
261 dma-names = "rx-tx";
263 bus-width = <4>;
264 cap-sd-highspeed;
265 sd-uhs-sdr12;
266 sd-uhs-sdr25;
267 sd-uhs-sdr50;
271 compatible = "socionext,uniphier-sd-v2.91";
275 pinctrl-names = "default";
276 pinctrl-0 = <&pinctrl_emmc>;
278 reset-names = "host", "bridge", "hw";
280 dma-names = "rx-tx";
282 bus-width = <8>;
283 cap-mmc-highspeed;
284 cap-mmc-hw-reset;
285 non-removable;
289 compatible = "socionext,uniphier-ehci", "generic-ehci";
293 pinctrl-names = "default";
294 pinctrl-0 = <&pinctrl_usb0>;
299 has-transaction-translator;
303 compatible = "socionext,uniphier-ehci", "generic-ehci";
307 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_usb1>;
313 has-transaction-translator;
317 compatible = "socionext,uniphier-ehci", "generic-ehci";
321 pinctrl-names = "default";
322 pinctrl-0 = <&pinctrl_usb2>;
327 has-transaction-translator;
330 soc-glue@5f800000 {
331 compatible = "socionext,uniphier-ld4-soc-glue",
332 "simple-mfd", "syscon";
336 compatible = "socionext,uniphier-ld4-pinctrl";
340 soc-glue@5f900000 {
341 compatible = "socionext,uniphier-ld4-soc-glue-debug",
342 "simple-mfd";
343 #address-cells = <1>;
344 #size-cells = <1>;
348 compatible = "socionext,uniphier-efuse";
353 compatible = "socionext,uniphier-efuse";
359 compatible = "arm,cortex-a9-global-timer";
366 compatible = "arm,cortex-a9-twd-timer";
372 intc: interrupt-controller@60001000 {
373 compatible = "arm,cortex-a9-gic";
376 #interrupt-cells = <3>;
377 interrupt-controller;
380 aidet: interrupt-controller@61830000 {
381 compatible = "socionext,uniphier-ld4-aidet";
383 interrupt-controller;
384 #interrupt-cells = <2>;
388 compatible = "socionext,uniphier-ld4-sysctrl",
389 "simple-mfd", "syscon";
393 compatible = "socionext,uniphier-ld4-clock";
394 #clock-cells = <1>;
398 compatible = "socionext,uniphier-ld4-reset";
399 #reset-cells = <1>;
403 nand: nand-controller@68000000 {
404 compatible = "socionext,uniphier-denali-nand-v5a";
406 reg-names = "nand_data", "denali_reg";
408 #address-cells = <1>;
409 #size-cells = <0>;
411 pinctrl-names = "default";
412 pinctrl-0 = <&pinctrl_nand>;
413 clock-names = "nand", "nand_x", "ecc";
415 reset-names = "nand", "reg";
421 #include "uniphier-pinctrl.dtsi"