Lines Matching +full:sun6i +full:- +full:a31 +full:- +full:ccu
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/clock/sun8i-de2.h>
44 #include <dt-bindings/clock/sun8i-h3-ccu.h>
45 #include <dt-bindings/clock/sun8i-r-ccu.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/reset/sun8i-de2.h>
48 #include <dt-bindings/reset/sun8i-h3-ccu.h>
49 #include <dt-bindings/reset/sun8i-r-ccu.h>
52 interrupt-parent = <&gic>;
53 #address-cells = <1>;
54 #size-cells = <1>;
57 #address-cells = <1>;
58 #size-cells = <1>;
61 framebuffer-hdmi {
62 compatible = "allwinner,simple-framebuffer",
63 "simple-framebuffer";
64 allwinner,pipeline = "mixer0-lcd0-hdmi";
66 <&ccu CLK_TCON0>, <&ccu CLK_HDMI>;
70 framebuffer-tve {
71 compatible = "allwinner,simple-framebuffer",
72 "simple-framebuffer";
73 allwinner,pipeline = "mixer1-lcd1-tve";
75 <&ccu CLK_TVE>;
81 #address-cells = <1>;
82 #size-cells = <1>;
86 #clock-cells = <0>;
87 compatible = "fixed-clock";
88 clock-frequency = <24000000>;
89 clock-accuracy = <50000>;
90 clock-output-names = "osc24M";
94 #clock-cells = <0>;
95 compatible = "fixed-clock";
96 clock-frequency = <32768>;
97 clock-accuracy = <50000>;
98 clock-output-names = "ext_osc32k";
102 de: display-engine {
103 compatible = "allwinner,sun8i-h3-display-engine";
109 compatible = "simple-bus";
110 #address-cells = <1>;
111 #size-cells = <1>;
112 dma-ranges;
118 clocks = <&ccu CLK_BUS_DE>,
119 <&ccu CLK_DE>;
120 clock-names = "bus",
122 resets = <&ccu RST_BUS_DE>;
123 #clock-cells = <1>;
124 #reset-cells = <1>;
128 compatible = "allwinner,sun8i-h3-de2-mixer-0";
132 clock-names = "bus",
137 #address-cells = <1>;
138 #size-cells = <0>;
144 remote-endpoint = <&tcon0_in_mixer0>;
150 dma: dma-controller@1c02000 {
151 compatible = "allwinner,sun8i-h3-dma";
154 clocks = <&ccu CLK_BUS_DMA>;
155 resets = <&ccu RST_BUS_DMA>;
156 #dma-cells = <1>;
159 tcon0: lcd-controller@1c0c000 {
160 compatible = "allwinner,sun8i-h3-tcon-tv",
161 "allwinner,sun8i-a83t-tcon-tv";
164 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
165 clock-names = "ahb", "tcon-ch1";
166 resets = <&ccu RST_BUS_TCON0>;
167 reset-names = "lcd";
170 #address-cells = <1>;
171 #size-cells = <0>;
177 remote-endpoint = <&mixer0_out_tcon0>;
182 #address-cells = <1>;
183 #size-cells = <0>;
188 remote-endpoint = <&hdmi_in_tcon0>;
197 pinctrl-names = "default";
198 pinctrl-0 = <&mmc0_pins>;
199 resets = <&ccu RST_BUS_MMC0>;
200 reset-names = "ahb";
203 #address-cells = <1>;
204 #size-cells = <0>;
210 pinctrl-names = "default";
211 pinctrl-0 = <&mmc1_pins>;
212 resets = <&ccu RST_BUS_MMC1>;
213 reset-names = "ahb";
216 #address-cells = <1>;
217 #size-cells = <0>;
223 resets = <&ccu RST_BUS_MMC2>;
224 reset-names = "ahb";
227 #address-cells = <1>;
228 #size-cells = <0>;
234 #address-cells = <1>;
235 #size-cells = <1>;
237 ths_calibration: thermal-sensor-calibration@34 {
243 compatible = "allwinner,sun8i-h3-msgbox",
244 "allwinner,sun6i-a31-msgbox";
246 clocks = <&ccu CLK_BUS_MSGBOX>;
247 resets = <&ccu RST_BUS_MSGBOX>;
249 #mbox-cells = <1>;
253 compatible = "allwinner,sun8i-h3-musb";
255 clocks = <&ccu CLK_BUS_OTG>;
256 resets = <&ccu RST_BUS_OTG>;
258 interrupt-names = "mc";
260 phy-names = "usb";
267 compatible = "allwinner,sun8i-h3-usb-phy";
273 reg-names = "phy_ctrl",
278 clocks = <&ccu CLK_USB_PHY0>,
279 <&ccu CLK_USB_PHY1>,
280 <&ccu CLK_USB_PHY2>,
281 <&ccu CLK_USB_PHY3>;
282 clock-names = "usb0_phy",
286 resets = <&ccu RST_USB_PHY0>,
287 <&ccu RST_USB_PHY1>,
288 <&ccu RST_USB_PHY2>,
289 <&ccu RST_USB_PHY3>;
290 reset-names = "usb0_reset",
295 #phy-cells = <1>;
299 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
302 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
303 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
308 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
311 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
312 <&ccu CLK_USB_OHCI0>;
313 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
318 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
321 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
322 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
324 phy-names = "usb";
329 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
332 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
333 <&ccu CLK_USB_OHCI1>;
334 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
336 phy-names = "usb";
341 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
344 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
345 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
347 phy-names = "usb";
352 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
355 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
356 <&ccu CLK_USB_OHCI2>;
357 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
359 phy-names = "usb";
364 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
367 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
368 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
370 phy-names = "usb";
375 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
378 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
379 <&ccu CLK_USB_OHCI3>;
380 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
382 phy-names = "usb";
386 ccu: clock@1c20000 { label
390 clock-names = "hosc", "losc";
391 #clock-cells = <1>;
392 #reset-cells = <1>;
400 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
401 clock-names = "apb", "hosc", "losc";
402 gpio-controller;
403 #gpio-cells = <3>;
404 interrupt-controller;
405 #interrupt-cells = <3>;
407 csi_pins: csi-pins {
414 emac_rgmii_pins: emac-rgmii-pins {
419 drive-strength = <40>;
422 i2c0_pins: i2c0-pins {
427 i2c1_pins: i2c1-pins {
432 i2c2_pins: i2c2-pins {
437 mmc0_pins: mmc0-pins {
441 drive-strength = <30>;
442 bias-pull-up;
445 mmc1_pins: mmc1-pins {
449 drive-strength = <30>;
450 bias-pull-up;
453 mmc2_8bit_pins: mmc2-8bit-pins {
459 drive-strength = <30>;
460 bias-pull-up;
463 spdif_tx_pin: spdif-tx-pin {
468 spi0_pins: spi0-pins {
473 spi1_pins: spi1-pins {
478 uart0_pa_pins: uart0-pa-pins {
483 uart1_pins: uart1-pins {
488 uart1_rts_cts_pins: uart1-rts-cts-pins {
493 uart2_pins: uart2-pins {
498 uart2_rts_cts_pins: uart2-rts-cts-pins {
503 uart3_pins: uart3-pins {
508 uart3_rts_cts_pins: uart3-rts-cts-pins {
515 compatible = "allwinner,sun8i-a23-timer";
523 compatible = "allwinner,sun8i-h3-emac";
527 interrupt-names = "macirq";
528 resets = <&ccu RST_BUS_EMAC>;
529 reset-names = "stmmaceth";
530 clocks = <&ccu CLK_BUS_EMAC>;
531 clock-names = "stmmaceth";
535 #address-cells = <1>;
536 #size-cells = <0>;
537 compatible = "snps,dwmac-mdio";
540 mdio-mux {
541 compatible = "allwinner,sun8i-h3-mdio-mux";
542 #address-cells = <1>;
543 #size-cells = <0>;
545 mdio-parent-bus = <&mdio>;
548 compatible = "allwinner,sun8i-h3-mdio-internal";
550 #address-cells = <1>;
551 #size-cells = <0>;
553 int_mii_phy: ethernet-phy@1 {
554 compatible = "ethernet-phy-ieee802.3-c22";
556 clocks = <&ccu CLK_BUS_EPHY>;
557 resets = <&ccu RST_BUS_EPHY>;
563 #address-cells = <1>;
564 #size-cells = <0>;
569 mbus: dram-controller@1c62000 {
570 compatible = "allwinner,sun8i-h3-mbus";
572 clocks = <&ccu CLK_MBUS>;
573 #address-cells = <1>;
574 #size-cells = <1>;
575 dma-ranges = <0x00000000 0x40000000 0xc0000000>;
576 #interconnect-cells = <1>;
580 compatible = "allwinner,sun8i-h3-spi";
583 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
584 clock-names = "ahb", "mod";
586 dma-names = "rx", "tx";
587 pinctrl-names = "default";
588 pinctrl-0 = <&spi0_pins>;
589 resets = <&ccu RST_BUS_SPI0>;
591 #address-cells = <1>;
592 #size-cells = <0>;
596 compatible = "allwinner,sun8i-h3-spi";
599 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
600 clock-names = "ahb", "mod";
602 dma-names = "rx", "tx";
603 pinctrl-names = "default";
604 pinctrl-0 = <&spi1_pins>;
605 resets = <&ccu RST_BUS_SPI1>;
607 #address-cells = <1>;
608 #size-cells = <0>;
612 compatible = "allwinner,sun6i-a31-wdt";
619 #sound-dai-cells = <0>;
620 compatible = "allwinner,sun8i-h3-spdif";
623 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
624 resets = <&ccu RST_BUS_SPDIF>;
625 clock-names = "apb", "spdif";
627 dma-names = "tx";
632 compatible = "allwinner,sun8i-h3-pwm";
635 #pwm-cells = <3>;
640 #sound-dai-cells = <0>;
641 compatible = "allwinner,sun8i-h3-i2s";
644 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
645 clock-names = "apb", "mod";
647 resets = <&ccu RST_BUS_I2S0>;
648 dma-names = "rx", "tx";
653 #sound-dai-cells = <0>;
654 compatible = "allwinner,sun8i-h3-i2s";
657 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
658 clock-names = "apb", "mod";
660 resets = <&ccu RST_BUS_I2S1>;
661 dma-names = "rx", "tx";
666 #sound-dai-cells = <0>;
667 compatible = "allwinner,sun8i-h3-codec";
670 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
671 clock-names = "apb", "codec";
672 resets = <&ccu RST_BUS_CODEC>;
674 dma-names = "rx", "tx";
675 allwinner,codec-analog-controls = <&codec_analog>;
680 compatible = "snps,dw-apb-uart";
683 reg-shift = <2>;
684 reg-io-width = <4>;
685 clocks = <&ccu CLK_BUS_UART0>;
686 resets = <&ccu RST_BUS_UART0>;
688 dma-names = "rx", "tx";
693 compatible = "snps,dw-apb-uart";
696 reg-shift = <2>;
697 reg-io-width = <4>;
698 clocks = <&ccu CLK_BUS_UART1>;
699 resets = <&ccu RST_BUS_UART1>;
701 dma-names = "rx", "tx";
706 compatible = "snps,dw-apb-uart";
709 reg-shift = <2>;
710 reg-io-width = <4>;
711 clocks = <&ccu CLK_BUS_UART2>;
712 resets = <&ccu RST_BUS_UART2>;
714 dma-names = "rx", "tx";
719 compatible = "snps,dw-apb-uart";
722 reg-shift = <2>;
723 reg-io-width = <4>;
724 clocks = <&ccu CLK_BUS_UART3>;
725 resets = <&ccu RST_BUS_UART3>;
727 dma-names = "rx", "tx";
732 compatible = "allwinner,sun6i-a31-i2c";
735 clocks = <&ccu CLK_BUS_I2C0>;
736 resets = <&ccu RST_BUS_I2C0>;
737 pinctrl-names = "default";
738 pinctrl-0 = <&i2c0_pins>;
740 #address-cells = <1>;
741 #size-cells = <0>;
745 compatible = "allwinner,sun6i-a31-i2c";
748 clocks = <&ccu CLK_BUS_I2C1>;
749 resets = <&ccu RST_BUS_I2C1>;
750 pinctrl-names = "default";
751 pinctrl-0 = <&i2c1_pins>;
753 #address-cells = <1>;
754 #size-cells = <0>;
758 compatible = "allwinner,sun6i-a31-i2c";
761 clocks = <&ccu CLK_BUS_I2C2>;
762 resets = <&ccu RST_BUS_I2C2>;
763 pinctrl-names = "default";
764 pinctrl-0 = <&i2c2_pins>;
766 #address-cells = <1>;
767 #size-cells = <0>;
770 gic: interrupt-controller@1c81000 {
771 compatible = "arm,gic-400";
776 interrupt-controller;
777 #interrupt-cells = <3>;
782 compatible = "allwinner,sun8i-h3-csi";
785 clocks = <&ccu CLK_BUS_CSI>,
786 <&ccu CLK_CSI_SCLK>,
787 <&ccu CLK_DRAM_CSI>;
788 clock-names = "bus", "mod", "ram";
789 resets = <&ccu RST_BUS_CSI>;
790 pinctrl-names = "default";
791 pinctrl-0 = <&csi_pins>;
796 compatible = "allwinner,sun8i-h3-dw-hdmi",
797 "allwinner,sun8i-a83t-dw-hdmi";
799 reg-io-width = <1>;
801 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
802 <&ccu CLK_HDMI>;
803 clock-names = "iahb", "isfr", "tmds";
804 resets = <&ccu RST_BUS_HDMI1>;
805 reset-names = "ctrl";
807 phy-names = "phy";
811 #address-cells = <1>;
812 #size-cells = <0>;
818 remote-endpoint = <&tcon0_out_hdmi>;
828 hdmi_phy: hdmi-phy@1ef0000 {
829 compatible = "allwinner,sun8i-h3-hdmi-phy";
831 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
832 <&ccu CLK_PLL_VIDEO>;
833 clock-names = "bus", "mod", "pll-0";
834 resets = <&ccu RST_BUS_HDMI0>;
835 reset-names = "phy";
836 #phy-cells = <0>;
844 clock-output-names = "osc32k", "osc32k-out", "iosc";
846 #clock-cells = <1>;
850 compatible = "allwinner,sun8i-h3-r-ccu";
853 <&ccu CLK_PLL_PERIPH0>;
854 clock-names = "hosc", "losc", "iosc", "pll-periph";
855 #clock-cells = <1>;
856 #reset-cells = <1>;
859 codec_analog: codec-analog@1f015c0 {
860 compatible = "allwinner,sun8i-h3-codec-analog";
865 compatible = "allwinner,sun6i-a31-ir";
867 clock-names = "apb", "ir";
875 compatible = "allwinner,sun6i-a31-i2c";
878 pinctrl-names = "default";
879 pinctrl-0 = <&r_i2c_pins>;
883 #address-cells = <1>;
884 #size-cells = <0>;
888 compatible = "allwinner,sun8i-h3-r-pinctrl";
892 clock-names = "apb", "hosc", "losc";
893 gpio-controller;
894 #gpio-cells = <3>;
895 interrupt-controller;
896 #interrupt-cells = <3>;
898 r_ir_rx_pin: r-ir-rx-pin {
903 r_i2c_pins: r-i2c-pins {
908 r_pwm_pin: r-pwm-pin {
915 compatible = "allwinner,sun8i-h3-pwm";
917 pinctrl-names = "default";
918 pinctrl-0 = <&r_pwm_pin>;
920 #pwm-cells = <3>;