Lines Matching +full:arm926ej +full:- +full:s

1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
8 	#address-cells = <1>;
9 	#size-cells = <1>;
10 	interrupt-parent = <&intc>;
13 		osc24M: clk-24M {
14 			#clock-cells = <0>;
15 			compatible = "fixed-clock";
16 			clock-frequency = <24000000>;
17 			clock-output-names = "osc24M";
20 		osc32k: clk-32k {
21 			#clock-cells = <0>;
22 			compatible = "fixed-clock";
23 			clock-frequency = <32768>;
24 			clock-output-names = "osc32k";
30 			compatible = "arm,arm926ej-s";
36 		compatible = "simple-bus";
37 		#address-cells = <1>;
38 		#size-cells = <1>;
41 		sram-controller@1c00000 {
42 			compatible = "allwinner,suniv-f1c100s-system-control",
43 				     "allwinner,sun4i-a10-system-control";
45 			#address-cells = <1>;
46 			#size-cells = <1>;
50 				compatible = "mmio-sram";
52 				#address-cells = <1>;
53 				#size-cells = <1>;
56 				otg_sram: sram-section@0 {
57 					compatible = "allwinner,suniv-f1c100s-sram-d",
58 						     "allwinner,sun4i-a10-sram-d";
66 			compatible = "allwinner,suniv-f1c100s-ccu";
69 			clock-names = "hosc", "losc";
70 			#clock-cells = <1>;
71 			#reset-cells = <1>;
74 		intc: interrupt-controller@1c20400 {
75 			compatible = "allwinner,suniv-f1c100s-ic";
77 			interrupt-controller;
78 			#interrupt-cells = <1>;
82 			compatible = "allwinner,suniv-f1c100s-pinctrl";
86 			clock-names = "apb", "hosc", "losc";
87 			gpio-controller;
88 			interrupt-controller;
89 			#interrupt-cells = <3>;
90 			#gpio-cells = <3>;
92 			uart0_pe_pins: uart0-pe-pins {
99 			compatible = "allwinner,suniv-f1c100s-timer";
106 			compatible = "allwinner,suniv-f1c100s-wdt",
107 				     "allwinner,sun4i-a10-wdt";
112 			compatible = "snps,dw-apb-uart";
115 			reg-shift = <2>;
116 			reg-io-width = <4>;
123 			compatible = "snps,dw-apb-uart";
126 			reg-shift = <2>;
127 			reg-io-width = <4>;
134 			compatible = "snps,dw-apb-uart";
137 			reg-shift = <2>;
138 			reg-io-width = <4>;