Lines Matching +full:0 +full:x01cb4000

70 		#size-cells = <0>;
72 		cpu@0 {
75 			reg = <0>;
100 			#clock-cells = <0>;
108 			#clock-cells = <0>;
124 			reg = <0x01000000 0x10000>;
136 			reg = <0x01100000 0x100000>;
137 			clocks = <&display_clocks 0>,
141 			resets = <&display_clocks 0>;
145 				#size-cells = <0>;
160 			reg = <0x01c00000 0x1000>;
168 			reg = <0x01c0c000 0x1000>;
175 			#clock-cells = <0>;
182 				#size-cells = <0>;
184 				tcon0_in: port@0 {
185 					reg = <0>;
194 					#size-cells = <0>;
203 			reg = <0x01c0f000 0x1000>;
216 			pinctrl-0 = <&mmc0_pins>;
219 			#size-cells = <0>;
224 			reg = <0x01c10000 0x1000>;
237 			pinctrl-0 = <&mmc1_pins>;
240 			#size-cells = <0>;
245 			reg = <0x01c11000 0x1000>;
259 			#size-cells = <0>;
265 			reg = <0x01c15000 0x1000>;
275 			reg = <0x01c19000 0x0400>;
280 			phys = <&usbphy 0>;
282 			extcon = <&usbphy 0>;
288 			reg = <0x01c19400 0x2c>,
289 			      <0x01c1a800 0x4>;
302 			reg = <0x01c20000 0x400>;
303 			clocks = <&osc24M>, <&rtc 0>;
312 			reg = <0x01c20400 0x54>;
321 			reg = <0x01c20800 0x400>;
324 			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
390 			reg = <0x01c20c00 0xa0>;
399 			reg = <0x01c20ca0 0x20>;
406 			reg = <0x01c22800 0x400>;
413 			reg = <0x01c28000 0x400>;
414 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
424 			reg = <0x01c28400 0x400>;
435 			reg = <0x01c28800 0x400>;
441 			pinctrl-0 = <&uart2_pins>;
448 			reg = <0x01c2ac00 0x400>;
453 			pinctrl-0 = <&i2c0_pins>;
456 			#size-cells = <0>;
461 			reg = <0x01c2b000 0x400>;
467 			#size-cells = <0>;
473 			reg = <0x01c30000 0x10000>;
486 				#size-cells = <0>;
493 				#size-cells = <0>;
501 					#size-cells = <0>;
515 			reg = <0x01c68000 0x1000>;
520 			pinctrl-0 = <&spi0_pins>;
524 			#size-cells = <0>;
529 			reg = <0x01cb4000 0x3000>;
541 			reg = <0x01c81000 0x1000>,
542 			      <0x01c82000 0x2000>,
543 			      <0x01c84000 0x2000>,
544 			      <0x01c86000 0x2000>;