Lines Matching +full:sun6i +full:- +full:a31 +full:- +full:ccu
2 * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/interrupt-controller/arm-gic.h>
45 #include <dt-bindings/clock/sun8i-de2.h>
46 #include <dt-bindings/clock/sun8i-r40-ccu.h>
47 #include <dt-bindings/clock/sun8i-tcon-top.h>
48 #include <dt-bindings/reset/sun8i-r40-ccu.h>
49 #include <dt-bindings/reset/sun8i-de2.h>
50 #include <dt-bindings/thermal/thermal.h>
53 #address-cells = <1>;
54 #size-cells = <1>;
55 interrupt-parent = <&gic>;
58 #address-cells = <1>;
59 #size-cells = <1>;
63 #clock-cells = <0>;
64 compatible = "fixed-clock";
65 clock-frequency = <24000000>;
66 clock-accuracy = <50000>;
67 clock-output-names = "osc24M";
71 #clock-cells = <0>;
72 compatible = "fixed-clock";
73 clock-frequency = <32768>;
74 clock-accuracy = <20000>;
75 clock-output-names = "ext-osc32k";
80 #address-cells = <1>;
81 #size-cells = <0>;
84 compatible = "arm,cortex-a7";
90 compatible = "arm,cortex-a7";
96 compatible = "arm,cortex-a7";
102 compatible = "arm,cortex-a7";
108 de: display-engine {
109 compatible = "allwinner,sun8i-r40-display-engine";
114 thermal-zones {
115 cpu_thermal: cpu0-thermal {
117 polling-delay-passive = <0>;
118 polling-delay = <0>;
119 thermal-sensors = <&ths 0>;
122 gpu_thermal: gpu-thermal {
124 polling-delay-passive = <0>;
125 polling-delay = <0>;
126 thermal-sensors = <&ths 1>;
131 compatible = "simple-bus";
132 #address-cells = <1>;
133 #size-cells = <1>;
137 compatible = "allwinner,sun8i-r40-de2-clk",
138 "allwinner,sun8i-h3-de2-clk";
140 clocks = <&ccu CLK_BUS_DE>,
141 <&ccu CLK_DE>;
142 clock-names = "bus",
144 resets = <&ccu RST_BUS_DE>;
145 #clock-cells = <1>;
146 #reset-cells = <1>;
150 compatible = "allwinner,sun8i-r40-de2-mixer-0";
154 clock-names = "bus",
159 #address-cells = <1>;
160 #size-cells = <0>;
165 remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
172 compatible = "allwinner,sun8i-r40-de2-mixer-1";
176 clock-names = "bus",
181 #address-cells = <1>;
182 #size-cells = <0>;
187 remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
193 syscon: system-control@1c00000 {
194 compatible = "allwinner,sun8i-r40-system-control",
195 "allwinner,sun4i-a10-system-control";
197 #address-cells = <1>;
198 #size-cells = <1>;
202 compatible = "mmio-sram";
204 #address-cells = <1>;
205 #size-cells = <1>;
208 ve_sram: sram-section@0 {
209 compatible = "allwinner,sun8i-r40-sram-c1",
210 "allwinner,sun4i-a10-sram-c1";
216 nmi_intc: interrupt-controller@1c00030 {
217 compatible = "allwinner,sun7i-a20-sc-nmi";
218 interrupt-controller;
219 #interrupt-cells = <2>;
224 dma: dma-controller@1c02000 {
225 compatible = "allwinner,sun8i-r40-dma",
226 "allwinner,sun50i-a64-dma";
229 clocks = <&ccu CLK_BUS_DMA>;
230 dma-channels = <16>;
231 dma-requests = <31>;
232 resets = <&ccu RST_BUS_DMA>;
233 #dma-cells = <1>;
237 compatible = "allwinner,sun8i-r40-spi",
238 "allwinner,sun8i-h3-spi";
241 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
242 clock-names = "ahb", "mod";
243 resets = <&ccu RST_BUS_SPI0>;
245 #address-cells = <1>;
246 #size-cells = <0>;
250 compatible = "allwinner,sun8i-r40-spi",
251 "allwinner,sun8i-h3-spi";
254 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
255 clock-names = "ahb", "mod";
256 resets = <&ccu RST_BUS_SPI1>;
258 #address-cells = <1>;
259 #size-cells = <0>;
263 compatible = "allwinner,sun8i-r40-csi0",
264 "allwinner,sun7i-a20-csi0";
267 clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>,
268 <&ccu CLK_DRAM_CSI0>;
269 clock-names = "bus", "isp", "ram";
270 resets = <&ccu RST_BUS_CSI0>;
272 interconnect-names = "dma-mem";
276 video-codec@1c0e000 {
277 compatible = "allwinner,sun8i-r40-video-engine";
279 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
280 <&ccu CLK_DRAM_VE>;
281 clock-names = "ahb", "mod", "ram";
282 resets = <&ccu RST_BUS_VE>;
288 compatible = "allwinner,sun8i-r40-mmc",
289 "allwinner,sun50i-a64-mmc";
291 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
292 clock-names = "ahb", "mmc";
293 resets = <&ccu RST_BUS_MMC0>;
294 reset-names = "ahb";
295 pinctrl-0 = <&mmc0_pins>;
296 pinctrl-names = "default";
299 #address-cells = <1>;
300 #size-cells = <0>;
304 compatible = "allwinner,sun8i-r40-mmc",
305 "allwinner,sun50i-a64-mmc";
307 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
308 clock-names = "ahb", "mmc";
309 resets = <&ccu RST_BUS_MMC1>;
310 reset-names = "ahb";
313 #address-cells = <1>;
314 #size-cells = <0>;
318 compatible = "allwinner,sun8i-r40-emmc",
319 "allwinner,sun50i-a64-emmc";
321 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
322 clock-names = "ahb", "mmc";
323 resets = <&ccu RST_BUS_MMC2>;
324 reset-names = "ahb";
325 pinctrl-0 = <&mmc2_pins>;
326 pinctrl-names = "default";
329 #address-cells = <1>;
330 #size-cells = <0>;
334 compatible = "allwinner,sun8i-r40-mmc",
335 "allwinner,sun50i-a64-mmc";
337 clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;
338 clock-names = "ahb", "mmc";
339 resets = <&ccu RST_BUS_MMC3>;
340 reset-names = "ahb";
343 #address-cells = <1>;
344 #size-cells = <0>;
348 compatible = "allwinner,sun8i-r40-usb-phy";
353 reg-names = "phy_ctrl",
357 clocks = <&ccu CLK_USB_PHY0>,
358 <&ccu CLK_USB_PHY1>,
359 <&ccu CLK_USB_PHY2>;
360 clock-names = "usb0_phy",
363 resets = <&ccu RST_USB_PHY0>,
364 <&ccu RST_USB_PHY1>,
365 <&ccu RST_USB_PHY2>;
366 reset-names = "usb0_reset",
370 #phy-cells = <1>;
374 compatible = "allwinner,sun8i-r40-crypto";
377 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
378 clock-names = "bus", "mod";
379 resets = <&ccu RST_BUS_CE>;
383 compatible = "allwinner,sun8i-r40-spi",
384 "allwinner,sun8i-h3-spi";
387 clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
388 clock-names = "ahb", "mod";
389 resets = <&ccu RST_BUS_SPI2>;
391 #address-cells = <1>;
392 #size-cells = <0>;
396 compatible = "allwinner,sun8i-r40-ahci";
399 clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
400 resets = <&ccu RST_BUS_SATA>;
401 reset-names = "ahci";
406 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
409 clocks = <&ccu CLK_BUS_EHCI1>;
410 resets = <&ccu RST_BUS_EHCI1>;
412 phy-names = "usb";
417 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
420 clocks = <&ccu CLK_BUS_OHCI1>,
421 <&ccu CLK_USB_OHCI1>;
422 resets = <&ccu RST_BUS_OHCI1>;
424 phy-names = "usb";
429 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
432 clocks = <&ccu CLK_BUS_EHCI2>;
433 resets = <&ccu RST_BUS_EHCI2>;
435 phy-names = "usb";
440 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
443 clocks = <&ccu CLK_BUS_OHCI2>,
444 <&ccu CLK_USB_OHCI2>;
445 resets = <&ccu RST_BUS_OHCI2>;
447 phy-names = "usb";
452 compatible = "allwinner,sun8i-r40-spi",
453 "allwinner,sun8i-h3-spi";
456 clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
457 clock-names = "ahb", "mod";
458 resets = <&ccu RST_BUS_SPI3>;
460 #address-cells = <1>;
461 #size-cells = <0>;
464 ccu: clock@1c20000 { label
465 compatible = "allwinner,sun8i-r40-ccu";
468 clock-names = "hosc", "losc";
469 #clock-cells = <1>;
470 #reset-cells = <1>;
474 compatible = "allwinner,sun8i-r40-rtc";
477 clock-output-names = "osc32k", "osc32k-out";
479 #clock-cells = <1>;
483 compatible = "allwinner,sun8i-r40-pinctrl";
486 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
487 clock-names = "apb", "hosc", "losc";
488 gpio-controller;
489 interrupt-controller;
490 #interrupt-cells = <3>;
491 #gpio-cells = <3>;
493 clk_out_a_pin: clk-out-a-pin {
498 /omit-if-no-ref/
499 csi0_8bits_pins: csi0-8bits-pins {
506 /omit-if-no-ref/
507 csi0_mclk_pin: csi0-mclk-pin {
512 gmac_rgmii_pins: gmac-rgmii-pins {
522 drive-strength = <40>;
525 i2c0_pins: i2c0-pins {
530 i2c1_pins: i2c1-pins {
535 i2c2_pins: i2c2-pins {
540 i2c3_pins: i2c3-pins {
545 i2c4_pins: i2c4-pins {
550 ir0_pins: ir0-pins {
555 ir1_pins: ir1-pins {
560 mmc0_pins: mmc0-pins {
564 drive-strength = <30>;
565 bias-pull-up;
568 mmc1_pg_pins: mmc1-pg-pins {
572 drive-strength = <30>;
573 bias-pull-up;
576 mmc2_pins: mmc2-pins {
581 drive-strength = <30>;
582 bias-pull-up;
585 /omit-if-no-ref/
586 spi0_pc_pins: spi0-pc-pins {
591 /omit-if-no-ref/
592 spi0_cs0_pc_pin: spi0-cs0-pc-pin {
597 /omit-if-no-ref/
598 spi1_pi_pins: spi1-pi-pins {
603 /omit-if-no-ref/
604 spi1_cs0_pi_pin: spi1-cs0-pi-pin {
609 /omit-if-no-ref/
610 spi1_cs1_pi_pin: spi1-cs1-pi-pin {
615 uart0_pb_pins: uart0-pb-pins {
620 uart3_pg_pins: uart3-pg-pins {
625 uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
632 compatible = "allwinner,sun4i-a10-wdt";
639 compatible = "allwinner,sun8i-r40-ir",
640 "allwinner,sun6i-a31-ir";
642 pinctrl-0 = <&ir0_pins>;
643 pinctrl-names = "default";
644 clocks = <&ccu CLK_BUS_IR0>, <&ccu CLK_IR0>;
645 clock-names = "apb", "ir";
647 resets = <&ccu RST_BUS_IR0>;
652 compatible = "allwinner,sun8i-r40-ir",
653 "allwinner,sun6i-a31-ir";
655 pinctrl-0 = <&ir1_pins>;
656 pinctrl-names = "default";
657 clocks = <&ccu CLK_BUS_IR1>, <&ccu CLK_IR1>;
658 clock-names = "apb", "ir";
660 resets = <&ccu RST_BUS_IR1>;
664 ths: thermal-sensor@1c24c00 {
665 compatible = "allwinner,sun8i-r40-ths";
667 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
668 clock-names = "bus", "mod";
670 resets = <&ccu RST_BUS_THS>;
671 /* TODO: add nvmem-cells for calibration */
672 #thermal-sensor-cells = <1>;
676 compatible = "snps,dw-apb-uart";
679 reg-shift = <2>;
680 reg-io-width = <4>;
681 clocks = <&ccu CLK_BUS_UART0>;
682 resets = <&ccu RST_BUS_UART0>;
687 compatible = "snps,dw-apb-uart";
690 reg-shift = <2>;
691 reg-io-width = <4>;
692 clocks = <&ccu CLK_BUS_UART1>;
693 resets = <&ccu RST_BUS_UART1>;
698 compatible = "snps,dw-apb-uart";
701 reg-shift = <2>;
702 reg-io-width = <4>;
703 clocks = <&ccu CLK_BUS_UART2>;
704 resets = <&ccu RST_BUS_UART2>;
709 compatible = "snps,dw-apb-uart";
712 reg-shift = <2>;
713 reg-io-width = <4>;
714 clocks = <&ccu CLK_BUS_UART3>;
715 resets = <&ccu RST_BUS_UART3>;
720 compatible = "snps,dw-apb-uart";
723 reg-shift = <2>;
724 reg-io-width = <4>;
725 clocks = <&ccu CLK_BUS_UART4>;
726 resets = <&ccu RST_BUS_UART4>;
731 compatible = "snps,dw-apb-uart";
734 reg-shift = <2>;
735 reg-io-width = <4>;
736 clocks = <&ccu CLK_BUS_UART5>;
737 resets = <&ccu RST_BUS_UART5>;
742 compatible = "snps,dw-apb-uart";
745 reg-shift = <2>;
746 reg-io-width = <4>;
747 clocks = <&ccu CLK_BUS_UART6>;
748 resets = <&ccu RST_BUS_UART6>;
753 compatible = "snps,dw-apb-uart";
756 reg-shift = <2>;
757 reg-io-width = <4>;
758 clocks = <&ccu CLK_BUS_UART7>;
759 resets = <&ccu RST_BUS_UART7>;
764 compatible = "allwinner,sun6i-a31-i2c";
767 clocks = <&ccu CLK_BUS_I2C0>;
768 resets = <&ccu RST_BUS_I2C0>;
769 pinctrl-0 = <&i2c0_pins>;
770 pinctrl-names = "default";
772 #address-cells = <1>;
773 #size-cells = <0>;
777 compatible = "allwinner,sun6i-a31-i2c";
780 clocks = <&ccu CLK_BUS_I2C1>;
781 resets = <&ccu RST_BUS_I2C1>;
782 pinctrl-0 = <&i2c1_pins>;
783 pinctrl-names = "default";
785 #address-cells = <1>;
786 #size-cells = <0>;
790 compatible = "allwinner,sun6i-a31-i2c";
793 clocks = <&ccu CLK_BUS_I2C2>;
794 resets = <&ccu RST_BUS_I2C2>;
795 pinctrl-0 = <&i2c2_pins>;
796 pinctrl-names = "default";
798 #address-cells = <1>;
799 #size-cells = <0>;
803 compatible = "allwinner,sun6i-a31-i2c";
806 clocks = <&ccu CLK_BUS_I2C3>;
807 resets = <&ccu RST_BUS_I2C3>;
808 pinctrl-0 = <&i2c3_pins>;
809 pinctrl-names = "default";
811 #address-cells = <1>;
812 #size-cells = <0>;
816 compatible = "allwinner,sun6i-a31-i2c";
819 clocks = <&ccu CLK_BUS_I2C4>;
820 resets = <&ccu RST_BUS_I2C4>;
821 pinctrl-0 = <&i2c4_pins>;
822 pinctrl-names = "default";
824 #address-cells = <1>;
825 #size-cells = <0>;
829 compatible = "allwinner,sun8i-r40-mali", "arm,mali-400";
838 interrupt-names = "gp",
845 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
846 clock-names = "bus", "core";
847 resets = <&ccu RST_BUS_GPU>;
851 compatible = "allwinner,sun8i-r40-gmac";
852 syscon = <&ccu>;
855 interrupt-names = "macirq";
856 resets = <&ccu RST_BUS_GMAC>;
857 reset-names = "stmmaceth";
858 clocks = <&ccu CLK_BUS_GMAC>;
859 clock-names = "stmmaceth";
863 compatible = "snps,dwmac-mdio";
864 #address-cells = <1>;
865 #size-cells = <0>;
869 mbus: dram-controller@1c62000 {
870 compatible = "allwinner,sun8i-r40-mbus";
872 clocks = <&ccu 155>;
873 #address-cells = <1>;
874 #size-cells = <1>;
875 dma-ranges = <0x00000000 0x40000000 0x80000000>;
876 #interconnect-cells = <1>;
879 tcon_top: tcon-top@1c70000 {
880 compatible = "allwinner,sun8i-r40-tcon-top";
882 clocks = <&ccu CLK_BUS_TCON_TOP>,
883 <&ccu CLK_TCON_TV0>,
884 <&ccu CLK_TVE0>,
885 <&ccu CLK_TCON_TV1>,
886 <&ccu CLK_TVE1>,
887 <&ccu CLK_DSI_DPHY>;
888 clock-names = "bus",
889 "tcon-tv0",
891 "tcon-tv1",
894 clock-output-names = "tcon-top-tv0",
895 "tcon-top-tv1",
896 "tcon-top-dsi";
897 resets = <&ccu RST_BUS_TCON_TOP>;
898 #clock-cells = <1>;
901 #address-cells = <1>;
902 #size-cells = <0>;
908 remote-endpoint = <&mixer0_out_tcon_top>;
913 #address-cells = <1>;
914 #size-cells = <0>;
927 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
932 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>;
937 #address-cells = <1>;
938 #size-cells = <0>;
943 remote-endpoint = <&mixer1_out_tcon_top>;
948 #address-cells = <1>;
949 #size-cells = <0>;
962 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
967 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>;
972 #address-cells = <1>;
973 #size-cells = <0>;
978 remote-endpoint = <&tcon_tv0_out_tcon_top>;
983 remote-endpoint = <&tcon_tv1_out_tcon_top>;
991 remote-endpoint = <&hdmi_in_tcon_top>;
997 tcon_tv0: lcd-controller@1c73000 {
998 compatible = "allwinner,sun8i-r40-tcon-tv";
1001 clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top CLK_TCON_TOP_TV0>;
1002 clock-names = "ahb", "tcon-ch1";
1003 resets = <&ccu RST_BUS_TCON_TV0>;
1004 reset-names = "lcd";
1008 #address-cells = <1>;
1009 #size-cells = <0>;
1012 #address-cells = <1>;
1013 #size-cells = <0>;
1018 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
1023 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
1028 #address-cells = <1>;
1029 #size-cells = <0>;
1034 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
1040 tcon_tv1: lcd-controller@1c74000 {
1041 compatible = "allwinner,sun8i-r40-tcon-tv";
1044 clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top CLK_TCON_TOP_TV1>;
1045 clock-names = "ahb", "tcon-ch1";
1046 resets = <&ccu RST_BUS_TCON_TV1>;
1047 reset-names = "lcd";
1051 #address-cells = <1>;
1052 #size-cells = <0>;
1055 #address-cells = <1>;
1056 #size-cells = <0>;
1061 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>;
1066 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>;
1071 #address-cells = <1>;
1072 #size-cells = <0>;
1077 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>;
1083 gic: interrupt-controller@1c81000 {
1084 compatible = "arm,gic-400";
1089 interrupt-controller;
1090 #interrupt-cells = <3>;
1095 compatible = "allwinner,sun8i-r40-dw-hdmi",
1096 "allwinner,sun8i-a83t-dw-hdmi";
1098 reg-io-width = <1>;
1100 clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>,
1101 <&ccu CLK_HDMI>;
1102 clock-names = "iahb", "isfr", "tmds";
1103 resets = <&ccu RST_BUS_HDMI1>;
1104 reset-names = "ctrl";
1106 phy-names = "phy";
1110 #address-cells = <1>;
1111 #size-cells = <0>;
1117 remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
1127 hdmi_phy: hdmi-phy@1ef0000 {
1128 compatible = "allwinner,sun8i-r40-hdmi-phy";
1130 clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>,
1131 <&ccu CLK_PLL_VIDEO0>, <&ccu CLK_PLL_VIDEO1>;
1132 clock-names = "bus", "mod", "pll-0", "pll-1";
1133 resets = <&ccu RST_BUS_HDMI0>;
1134 reset-names = "phy";
1135 #phy-cells = <0>;
1140 compatible = "arm,cortex-a7-pmu";
1145 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
1149 compatible = "arm,armv7-timer";