Lines Matching +full:0 +full:x01c02000
63 #clock-cells = <0>;
71 #clock-cells = <0>;
81 #size-cells = <0>;
83 cpu0: cpu@0 {
86 reg = <0>;
117 polling-delay-passive = <0>;
118 polling-delay = <0>;
119 thermal-sensors = <&ths 0>;
124 polling-delay-passive = <0>;
125 polling-delay = <0>;
139 reg = <0x01000000 0x10000>;
150 compatible = "allwinner,sun8i-r40-de2-mixer-0";
151 reg = <0x01100000 0x100000>;
160 #size-cells = <0>;
173 reg = <0x01200000 0x100000>;
182 #size-cells = <0>;
196 reg = <0x01c00000 0x30>;
203 reg = <0x01d00000 0xd0000>;
206 ranges = <0 0x01d00000 0xd0000>;
208 ve_sram: sram-section@0 {
211 reg = <0x000000 0x80000>;
220 reg = <0x01c00030 0x0c>;
221 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
227 reg = <0x01c02000 0x1000>;
239 reg = <0x01c05000 0x1000>;
246 #size-cells = <0>;
252 reg = <0x01c06000 0x1000>;
259 #size-cells = <0>;
265 reg = <0x01c09000 0x1000>;
278 reg = <0x01c0e000 0x1000>;
290 reg = <0x01c0f000 0x1000>;
295 pinctrl-0 = <&mmc0_pins>;
300 #size-cells = <0>;
306 reg = <0x01c10000 0x1000>;
314 #size-cells = <0>;
320 reg = <0x01c11000 0x1000>;
325 pinctrl-0 = <&mmc2_pins>;
330 #size-cells = <0>;
336 reg = <0x01c12000 0x1000>;
344 #size-cells = <0>;
349 reg = <0x01c13400 0x14>,
350 <0x01c14800 0x4>,
351 <0x01c19800 0x4>,
352 <0x01c1c800 0x4>;
375 reg = <0x01c15000 0x1000>;
385 reg = <0x01c17000 0x1000>;
392 #size-cells = <0>;
397 reg = <0x01c18000 0x1000>;
407 reg = <0x01c19000 0x100>;
418 reg = <0x01c19400 0x100>;
430 reg = <0x01c1c000 0x100>;
441 reg = <0x01c1c400 0x100>;
454 reg = <0x01c1f000 0x1000>;
461 #size-cells = <0>;
466 reg = <0x01c20000 0x400>;
467 clocks = <&osc24M>, <&rtc 0>;
475 reg = <0x01c20400 0x400>;
484 reg = <0x01c20800 0x400>;
486 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
633 reg = <0x01c20c90 0x10>;
641 reg = <0x01c21800 0x400>;
642 pinctrl-0 = <&ir0_pins>;
654 reg = <0x01c21c00 0x400>;
655 pinctrl-0 = <&ir1_pins>;
666 reg = <0x01c24c00 0x100>;
677 reg = <0x01c28000 0x400>;
688 reg = <0x01c28400 0x400>;
699 reg = <0x01c28800 0x400>;
710 reg = <0x01c28c00 0x400>;
721 reg = <0x01c29000 0x400>;
732 reg = <0x01c29400 0x400>;
743 reg = <0x01c29800 0x400>;
754 reg = <0x01c29c00 0x400>;
765 reg = <0x01c2ac00 0x400>;
769 pinctrl-0 = <&i2c0_pins>;
773 #size-cells = <0>;
778 reg = <0x01c2b000 0x400>;
782 pinctrl-0 = <&i2c1_pins>;
786 #size-cells = <0>;
791 reg = <0x01c2b400 0x400>;
795 pinctrl-0 = <&i2c2_pins>;
799 #size-cells = <0>;
804 reg = <0x01c2b800 0x400>;
808 pinctrl-0 = <&i2c3_pins>;
812 #size-cells = <0>;
817 reg = <0x01c2c000 0x400>;
821 pinctrl-0 = <&i2c4_pins>;
825 #size-cells = <0>;
830 reg = <0x01c40000 0x10000>;
853 reg = <0x01c50000 0x10000>;
865 #size-cells = <0>;
871 reg = <0x01c62000 0x1000>;
875 dma-ranges = <0x00000000 0x40000000 0x80000000>;
881 reg = <0x01c70000 0x1000>;
902 #size-cells = <0>;
904 tcon_top_mixer0_in: port@0 {
905 reg = <0>;
914 #size-cells = <0>;
917 tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
918 reg = <0>;
938 #size-cells = <0>;
949 #size-cells = <0>;
952 tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
953 reg = <0>;
973 #size-cells = <0>;
976 tcon_top_hdmi_in_tcon_tv0: endpoint@0 {
977 reg = <0>;
999 reg = <0x01c73000 0x1000>;
1009 #size-cells = <0>;
1011 tcon_tv0_in: port@0 {
1013 #size-cells = <0>;
1014 reg = <0>;
1016 tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
1017 reg = <0>;
1029 #size-cells = <0>;
1042 reg = <0x01c74000 0x1000>;
1052 #size-cells = <0>;
1054 tcon_tv1_in: port@0 {
1056 #size-cells = <0>;
1057 reg = <0>;
1059 tcon_tv1_in_tcon_top_mixer0: endpoint@0 {
1060 reg = <0>;
1072 #size-cells = <0>;
1085 reg = <0x01c81000 0x1000>,
1086 <0x01c82000 0x2000>,
1087 <0x01c84000 0x2000>,
1088 <0x01c86000 0x2000>;
1097 reg = <0x01ee0000 0x10000>;
1111 #size-cells = <0>;
1113 hdmi_in: port@0 {
1114 reg = <0>;
1129 reg = <0x01ef0000 0x10000>;
1132 clock-names = "bus", "mod", "pll-0", "pll-1";
1135 #phy-cells = <0>;