Lines Matching +full:sun6i +full:- +full:a31 +full:- +full:ccu
2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
48 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
51 interrupt-parent = <&gic>;
52 #address-cells = <1>;
53 #size-cells = <1>;
56 #address-cells = <1>;
57 #size-cells = <1>;
60 simplefb_lcd: framebuffer-lcd0 {
61 compatible = "allwinner,simple-framebuffer",
62 "simple-framebuffer";
63 allwinner,pipeline = "de_be0-lcd0";
64 clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>,
65 <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>,
66 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>;
71 de: display-engine {
78 compatible = "arm,armv7-timer";
83 clock-frequency = <24000000>;
84 arm,cpu-registers-not-fw-configured;
88 enable-method = "allwinner,sun8i-a23";
89 #address-cells = <1>;
90 #size-cells = <0>;
93 compatible = "arm,cortex-a7";
99 compatible = "arm,cortex-a7";
106 #address-cells = <1>;
107 #size-cells = <1>;
111 #clock-cells = <0>;
112 compatible = "fixed-clock";
113 clock-frequency = <24000000>;
114 clock-accuracy = <50000>;
115 clock-output-names = "osc24M";
119 #clock-cells = <0>;
120 compatible = "fixed-clock";
121 clock-frequency = <32768>;
122 clock-accuracy = <50000>;
123 clock-output-names = "ext-osc32k";
128 compatible = "simple-bus";
129 #address-cells = <1>;
130 #size-cells = <1>;
133 system-control@1c00000 {
134 compatible = "allwinner,sun8i-a23-system-control";
136 #address-cells = <1>;
137 #size-cells = <1>;
141 compatible = "mmio-sram";
143 #address-cells = <1>;
144 #size-cells = <1>;
147 ve_sram: sram-section@0 {
148 compatible = "allwinner,sun8i-a23-sram-c1",
149 "allwinner,sun4i-a10-sram-c1";
155 dma: dma-controller@1c02000 {
156 compatible = "allwinner,sun8i-a23-dma";
159 clocks = <&ccu CLK_BUS_DMA>;
160 resets = <&ccu RST_BUS_DMA>;
161 #dma-cells = <1>;
164 nfc: nand-controller@1c03000 {
165 compatible = "allwinner,sun8i-a23-nand-controller";
168 clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
169 clock-names = "ahb", "mod";
170 resets = <&ccu RST_BUS_NAND>;
171 reset-names = "ahb";
173 dma-names = "rxtx";
174 pinctrl-names = "default";
175 pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>;
177 #address-cells = <1>;
178 #size-cells = <0>;
181 tcon0: lcd-controller@1c0c000 {
186 clocks = <&ccu CLK_BUS_LCD>,
187 <&ccu CLK_LCD_CH0>,
188 <&ccu 13>;
189 clock-names = "ahb",
190 "tcon-ch0",
191 "lvds-alt";
192 clock-output-names = "tcon-pixel-clock";
193 #clock-cells = <0>;
194 resets = <&ccu RST_BUS_LCD>,
195 <&ccu RST_BUS_LVDS>;
196 reset-names = "lcd",
201 #address-cells = <1>;
202 #size-cells = <0>;
208 remote-endpoint = <&drc0_out_tcon0>;
219 compatible = "allwinner,sun7i-a20-mmc";
221 clocks = <&ccu CLK_BUS_MMC0>,
222 <&ccu CLK_MMC0>,
223 <&ccu CLK_MMC0_OUTPUT>,
224 <&ccu CLK_MMC0_SAMPLE>;
225 clock-names = "ahb",
229 resets = <&ccu RST_BUS_MMC0>;
230 reset-names = "ahb";
232 pinctrl-names = "default";
233 pinctrl-0 = <&mmc0_pins>;
235 #address-cells = <1>;
236 #size-cells = <0>;
240 compatible = "allwinner,sun7i-a20-mmc";
242 clocks = <&ccu CLK_BUS_MMC1>,
243 <&ccu CLK_MMC1>,
244 <&ccu CLK_MMC1_OUTPUT>,
245 <&ccu CLK_MMC1_SAMPLE>;
246 clock-names = "ahb",
250 resets = <&ccu RST_BUS_MMC1>;
251 reset-names = "ahb";
254 #address-cells = <1>;
255 #size-cells = <0>;
259 compatible = "allwinner,sun7i-a20-mmc";
261 clocks = <&ccu CLK_BUS_MMC2>,
262 <&ccu CLK_MMC2>,
263 <&ccu CLK_MMC2_OUTPUT>,
264 <&ccu CLK_MMC2_SAMPLE>;
265 clock-names = "ahb",
269 resets = <&ccu RST_BUS_MMC2>;
270 reset-names = "ahb";
273 #address-cells = <1>;
274 #size-cells = <0>;
280 clocks = <&ccu CLK_BUS_OTG>;
281 resets = <&ccu RST_BUS_OTG>;
283 interrupt-names = "mc";
285 phy-names = "usb";
296 clocks = <&ccu CLK_USB_PHY0>,
297 <&ccu CLK_USB_PHY1>;
298 clock-names = "usb0_phy",
300 resets = <&ccu RST_USB_PHY0>,
301 <&ccu RST_USB_PHY1>;
302 reset-names = "usb0_reset",
305 #phy-cells = <1>;
309 compatible = "allwinner,sun8i-a23-ehci", "generic-ehci";
312 clocks = <&ccu CLK_BUS_EHCI>;
313 resets = <&ccu RST_BUS_EHCI>;
315 phy-names = "usb";
320 compatible = "allwinner,sun8i-a23-ohci", "generic-ohci";
323 clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>;
324 resets = <&ccu RST_BUS_OHCI>;
326 phy-names = "usb";
330 ccu: clock@1c20000 { label
333 clock-names = "hosc", "losc";
334 #clock-cells = <1>;
335 #reset-cells = <1>;
342 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
343 clock-names = "apb", "hosc", "losc";
344 gpio-controller;
345 interrupt-controller;
346 #interrupt-cells = <3>;
347 #gpio-cells = <3>;
349 i2c0_pins: i2c0-pins {
354 i2c1_pins: i2c1-pins {
359 i2c2_pins: i2c2-pins {
364 lcd_rgb666_pins: lcd-rgb666-pins {
372 mmc0_pins: mmc0-pins {
376 drive-strength = <30>;
377 bias-pull-up;
380 mmc1_pg_pins: mmc1-pg-pins {
384 drive-strength = <30>;
385 bias-pull-up;
388 mmc2_8bit_pins: mmc2-8bit-pins {
394 drive-strength = <30>;
395 bias-pull-up;
398 nand_pins: nand-pins {
405 nand_cs0_pin: nand-cs0-pin {
408 bias-pull-up;
411 nand_cs1_pin: nand-cs1-pin {
414 bias-pull-up;
417 nand_rb0_pin: nand-rb0-pin {
420 bias-pull-up;
423 nand_rb1_pin: nand-rb1-pin {
426 bias-pull-up;
429 pwm0_pin: pwm0-pin {
434 uart0_pf_pins: uart0-pf-pins {
439 uart1_pg_pins: uart1-pg-pins {
444 uart1_cts_rts_pg_pins: uart1-cts-rts-pg-pins {
451 compatible = "allwinner,sun8i-a23-timer";
459 compatible = "allwinner,sun6i-a31-wdt";
466 compatible = "allwinner,sun7i-a20-pwm";
469 #pwm-cells = <3>;
474 compatible = "allwinner,sun4i-a10-lradc-keys";
481 compatible = "snps,dw-apb-uart";
484 reg-shift = <2>;
485 reg-io-width = <4>;
486 clocks = <&ccu CLK_BUS_UART0>;
487 resets = <&ccu RST_BUS_UART0>;
489 dma-names = "rx", "tx";
494 compatible = "snps,dw-apb-uart";
497 reg-shift = <2>;
498 reg-io-width = <4>;
499 clocks = <&ccu CLK_BUS_UART1>;
500 resets = <&ccu RST_BUS_UART1>;
502 dma-names = "rx", "tx";
507 compatible = "snps,dw-apb-uart";
510 reg-shift = <2>;
511 reg-io-width = <4>;
512 clocks = <&ccu CLK_BUS_UART2>;
513 resets = <&ccu RST_BUS_UART2>;
515 dma-names = "rx", "tx";
520 compatible = "snps,dw-apb-uart";
523 reg-shift = <2>;
524 reg-io-width = <4>;
525 clocks = <&ccu CLK_BUS_UART3>;
526 resets = <&ccu RST_BUS_UART3>;
528 dma-names = "rx", "tx";
533 compatible = "snps,dw-apb-uart";
536 reg-shift = <2>;
537 reg-io-width = <4>;
538 clocks = <&ccu CLK_BUS_UART4>;
539 resets = <&ccu RST_BUS_UART4>;
541 dma-names = "rx", "tx";
546 compatible = "allwinner,sun6i-a31-i2c";
549 clocks = <&ccu CLK_BUS_I2C0>;
550 resets = <&ccu RST_BUS_I2C0>;
551 pinctrl-names = "default";
552 pinctrl-0 = <&i2c0_pins>;
554 #address-cells = <1>;
555 #size-cells = <0>;
559 compatible = "allwinner,sun6i-a31-i2c";
562 clocks = <&ccu CLK_BUS_I2C1>;
563 resets = <&ccu RST_BUS_I2C1>;
564 pinctrl-names = "default";
565 pinctrl-0 = <&i2c1_pins>;
567 #address-cells = <1>;
568 #size-cells = <0>;
572 compatible = "allwinner,sun6i-a31-i2c";
575 clocks = <&ccu CLK_BUS_I2C2>;
576 resets = <&ccu RST_BUS_I2C2>;
577 pinctrl-names = "default";
578 pinctrl-0 = <&i2c2_pins>;
580 #address-cells = <1>;
581 #size-cells = <0>;
585 compatible = "allwinner,sun8i-a23-mali",
586 "allwinner,sun7i-a20-mali", "arm,mali-400";
595 interrupt-names = "gp",
602 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
603 clock-names = "bus", "core";
604 resets = <&ccu RST_BUS_GPU>;
605 #cooling-cells = <2>;
607 assigned-clocks = <&ccu CLK_GPU>;
608 assigned-clock-rates = <384000000>;
611 gic: interrupt-controller@1c81000 {
612 compatible = "arm,gic-400";
617 interrupt-controller;
618 #interrupt-cells = <3>;
622 fe0: display-frontend@1e00000 {
626 clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
627 <&ccu CLK_DRAM_DE_FE>;
628 clock-names = "ahb", "mod",
630 resets = <&ccu RST_BUS_DE_FE>;
633 #address-cells = <1>;
634 #size-cells = <0>;
640 remote-endpoint = <&be0_in_fe0>;
646 be0: display-backend@1e60000 {
650 clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
651 <&ccu CLK_DRAM_DE_BE>;
652 clock-names = "ahb", "mod",
654 resets = <&ccu RST_BUS_DE_BE>;
657 #address-cells = <1>;
658 #size-cells = <0>;
664 remote-endpoint = <&fe0_out_be0>;
672 remote-endpoint = <&drc0_in_be0>;
682 clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
683 <&ccu CLK_DRAM_DRC>;
684 clock-names = "ahb", "mod", "ram";
685 resets = <&ccu RST_BUS_DRC>;
688 #address-cells = <1>;
689 #size-cells = <0>;
695 remote-endpoint = <&be0_out_drc0>;
703 remote-endpoint = <&tcon0_in_drc0>;
710 compatible = "allwinner,sun8i-a23-rtc";
714 clock-output-names = "osc32k", "osc32k-out";
716 #clock-cells = <1>;
719 nmi_intc: interrupt-controller@1f00c00 {
720 compatible = "allwinner,sun6i-a31-r-intc";
721 interrupt-controller;
722 #interrupt-cells = <2>;
728 compatible = "allwinner,sun8i-a23-prcm";
732 compatible = "fixed-factor-clock";
733 #clock-cells = <0>;
734 clock-div = <1>;
735 clock-mult = <1>;
737 clock-output-names = "ar100";
741 compatible = "fixed-factor-clock";
742 #clock-cells = <0>;
743 clock-div = <1>;
744 clock-mult = <1>;
746 clock-output-names = "ahb0";
750 compatible = "allwinner,sun8i-a23-apb0-clk";
751 #clock-cells = <0>;
753 clock-output-names = "apb0";
757 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
758 #clock-cells = <1>;
760 clock-output-names = "apb0_pio", "apb0_timer",
766 compatible = "allwinner,sun6i-a31-clock-reset";
767 #reset-cells = <1>;
770 codec_analog: codec-analog {
771 compatible = "allwinner,sun8i-a23-codec-analog";
776 compatible = "allwinner,sun8i-a23-cpuconfig";
781 compatible = "snps,dw-apb-uart";
784 reg-shift = <2>;
785 reg-io-width = <4>;
792 compatible = "allwinner,sun8i-a23-i2c",
793 "allwinner,sun6i-a31-i2c";
796 pinctrl-names = "default";
797 pinctrl-0 = <&r_i2c_pins>;
801 #address-cells = <1>;
802 #size-cells = <0>;
806 compatible = "allwinner,sun8i-a23-r-pinctrl";
810 clock-names = "apb", "hosc", "losc";
812 gpio-controller;
813 interrupt-controller;
814 #interrupt-cells = <3>;
815 #gpio-cells = <3>;
817 r_i2c_pins: r-i2c-pins {
820 bias-pull-up;
823 r_rsb_pins: r-rsb-pins {
826 drive-strength = <20>;
827 bias-pull-up;
830 r_uart_pins_a: r-uart-pins {
837 compatible = "allwinner,sun8i-a23-rsb";
841 clock-frequency = <3000000>;
843 pinctrl-names = "default";
844 pinctrl-0 = <&r_rsb_pins>;
846 #address-cells = <1>;
847 #size-cells = <0>;