Lines Matching +full:sun4i +full:- +full:a10 +full:- +full:ccu
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include <dt-bindings/dma/sun4i-a10.h>
48 #include <dt-bindings/clock/sun7i-a20-ccu.h>
49 #include <dt-bindings/reset/sun4i-a10-ccu.h>
50 #include <dt-bindings/pinctrl/sun4i-a10.h>
53 interrupt-parent = <&gic>;
54 #address-cells = <1>;
55 #size-cells = <1>;
62 #address-cells = <1>;
63 #size-cells = <1>;
66 framebuffer-lcd0-hdmi {
67 compatible = "allwinner,simple-framebuffer",
68 "simple-framebuffer";
69 allwinner,pipeline = "de_be0-lcd0-hdmi";
70 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
71 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
72 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>,
73 <&ccu CLK_HDMI>;
77 framebuffer-lcd0 {
78 compatible = "allwinner,simple-framebuffer",
79 "simple-framebuffer";
80 allwinner,pipeline = "de_be0-lcd0";
81 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
82 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>,
83 <&ccu CLK_DRAM_DE_BE0>;
87 framebuffer-lcd0-tve0 {
88 compatible = "allwinner,simple-framebuffer",
89 "simple-framebuffer";
90 allwinner,pipeline = "de_be0-lcd0-tve0";
91 clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
92 <&ccu CLK_AHB_DE_BE0>,
93 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>,
94 <&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>;
100 #address-cells = <1>;
101 #size-cells = <0>;
104 compatible = "arm,cortex-a7";
107 clocks = <&ccu CLK_CPU>;
108 clock-latency = <244144>; /* 8 32k periods */
109 operating-points = <
119 #cooling-cells = <2>;
123 compatible = "arm,cortex-a7";
126 clocks = <&ccu CLK_CPU>;
127 clock-latency = <244144>; /* 8 32k periods */
128 operating-points = <
138 #cooling-cells = <2>;
142 thermal-zones {
145 polling-delay-passive = <250>;
146 polling-delay = <1000>;
147 thermal-sensors = <&rtp>;
149 cooling-maps {
152 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
175 reserved-memory {
176 #address-cells = <1>;
177 #size-cells = <1>;
181 default-pool {
182 compatible = "shared-dma-pool";
184 alloc-ranges = <0x40000000 0x10000000>;
186 linux,cma-default;
191 compatible = "arm,armv7-timer";
199 compatible = "arm,cortex-a7-pmu";
205 #address-cells = <1>;
206 #size-cells = <1>;
209 osc24M: clk-24M {
210 #clock-cells = <0>;
211 compatible = "fixed-clock";
212 clock-frequency = <24000000>;
213 clock-output-names = "osc24M";
216 osc32k: clk-32k {
217 #clock-cells = <0>;
218 compatible = "fixed-clock";
219 clock-frequency = <32768>;
220 clock-output-names = "osc32k";
227 * mode, using clk_set_rate auto-reparenting.
232 mii_phy_tx_clk: clk-mii-phy-tx {
233 #clock-cells = <0>;
234 compatible = "fixed-clock";
235 clock-frequency = <25000000>;
236 clock-output-names = "mii_phy_tx";
239 gmac_int_tx_clk: clk-gmac-int-tx {
240 #clock-cells = <0>;
241 compatible = "fixed-clock";
242 clock-frequency = <125000000>;
243 clock-output-names = "gmac_int_tx";
247 #clock-cells = <0>;
248 compatible = "allwinner,sun7i-a20-gmac-clk";
251 clock-output-names = "gmac_tx";
256 de: display-engine {
257 compatible = "allwinner,sun7i-a20-display-engine";
263 compatible = "simple-bus";
264 #address-cells = <1>;
265 #size-cells = <1>;
268 system-control@1c00000 {
269 compatible = "allwinner,sun7i-a20-system-control",
270 "allwinner,sun4i-a10-system-control";
272 #address-cells = <1>;
273 #size-cells = <1>;
277 compatible = "mmio-sram";
279 #address-cells = <1>;
280 #size-cells = <1>;
283 emac_sram: sram-section@8000 {
284 compatible = "allwinner,sun7i-a20-sram-a3-a4",
285 "allwinner,sun4i-a10-sram-a3-a4";
292 compatible = "mmio-sram";
294 #address-cells = <1>;
295 #size-cells = <1>;
298 otg_sram: sram-section@0 {
299 compatible = "allwinner,sun7i-a20-sram-d",
300 "allwinner,sun4i-a10-sram-d";
307 compatible = "mmio-sram";
309 #address-cells = <1>;
310 #size-cells = <1>;
313 ve_sram: sram-section@0 {
314 compatible = "allwinner,sun7i-a20-sram-c1",
315 "allwinner,sun4i-a10-sram-c1";
321 nmi_intc: interrupt-controller@1c00030 {
322 compatible = "allwinner,sun7i-a20-sc-nmi";
323 interrupt-controller;
324 #interrupt-cells = <2>;
329 dma: dma-controller@1c02000 {
330 compatible = "allwinner,sun4i-a10-dma";
333 clocks = <&ccu CLK_AHB_DMA>;
334 #dma-cells = <2>;
337 nfc: nand-controller@1c03000 {
338 compatible = "allwinner,sun4i-a10-nand";
341 clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
342 clock-names = "ahb", "mod";
344 dma-names = "rxtx";
346 #address-cells = <1>;
347 #size-cells = <0>;
351 compatible = "allwinner,sun4i-a10-spi";
354 clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
355 clock-names = "ahb", "mod";
358 dma-names = "rx", "tx";
360 #address-cells = <1>;
361 #size-cells = <0>;
362 num-cs = <4>;
366 compatible = "allwinner,sun4i-a10-spi";
369 clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
370 clock-names = "ahb", "mod";
373 dma-names = "rx", "tx";
375 #address-cells = <1>;
376 #size-cells = <0>;
377 num-cs = <1>;
381 compatible = "allwinner,sun7i-a20-csi0";
384 clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
385 clock-names = "bus", "isp", "ram";
386 resets = <&ccu RST_CSI0>;
391 compatible = "allwinner,sun4i-a10-emac";
394 clocks = <&ccu CLK_AHB_EMAC>;
400 compatible = "allwinner,sun4i-a10-mdio";
403 #address-cells = <1>;
404 #size-cells = <0>;
407 tcon0: lcd-controller@1c0c000 {
408 compatible = "allwinner,sun7i-a20-tcon0",
409 "allwinner,sun7i-a20-tcon";
412 resets = <&ccu RST_TCON0>, <&ccu RST_LVDS>;
413 reset-names = "lcd", "lvds";
414 clocks = <&ccu CLK_AHB_LCD0>,
415 <&ccu CLK_TCON0_CH0>,
416 <&ccu CLK_TCON0_CH1>;
417 clock-names = "ahb",
418 "tcon-ch0",
419 "tcon-ch1";
420 clock-output-names = "tcon0-pixel-clock";
421 #clock-cells = <0>;
425 #address-cells = <1>;
426 #size-cells = <0>;
429 #address-cells = <1>;
430 #size-cells = <0>;
435 remote-endpoint = <&be0_out_tcon0>;
440 remote-endpoint = <&be1_out_tcon0>;
445 #address-cells = <1>;
446 #size-cells = <0>;
451 remote-endpoint = <&hdmi_in_tcon0>;
452 allwinner,tcon-channel = <1>;
458 tcon1: lcd-controller@1c0d000 {
459 compatible = "allwinner,sun7i-a20-tcon1",
460 "allwinner,sun7i-a20-tcon";
463 resets = <&ccu RST_TCON1>;
464 reset-names = "lcd";
465 clocks = <&ccu CLK_AHB_LCD1>,
466 <&ccu CLK_TCON1_CH0>,
467 <&ccu CLK_TCON1_CH1>;
468 clock-names = "ahb",
469 "tcon-ch0",
470 "tcon-ch1";
471 clock-output-names = "tcon1-pixel-clock";
472 #clock-cells = <0>;
476 #address-cells = <1>;
477 #size-cells = <0>;
480 #address-cells = <1>;
481 #size-cells = <0>;
486 remote-endpoint = <&be0_out_tcon1>;
491 remote-endpoint = <&be1_out_tcon1>;
496 #address-cells = <1>;
497 #size-cells = <0>;
502 remote-endpoint = <&hdmi_in_tcon1>;
503 allwinner,tcon-channel = <1>;
509 video-codec@1c0e000 {
510 compatible = "allwinner,sun7i-a20-video-engine";
512 clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
513 <&ccu CLK_DRAM_VE>;
514 clock-names = "ahb", "mod", "ram";
515 resets = <&ccu RST_VE>;
521 compatible = "allwinner,sun7i-a20-mmc";
523 clocks = <&ccu CLK_AHB_MMC0>,
524 <&ccu CLK_MMC0>,
525 <&ccu CLK_MMC0_OUTPUT>,
526 <&ccu CLK_MMC0_SAMPLE>;
527 clock-names = "ahb",
532 pinctrl-names = "default";
533 pinctrl-0 = <&mmc0_pins>;
535 #address-cells = <1>;
536 #size-cells = <0>;
540 compatible = "allwinner,sun7i-a20-mmc";
542 clocks = <&ccu CLK_AHB_MMC1>,
543 <&ccu CLK_MMC1>,
544 <&ccu CLK_MMC1_OUTPUT>,
545 <&ccu CLK_MMC1_SAMPLE>;
546 clock-names = "ahb",
552 #address-cells = <1>;
553 #size-cells = <0>;
557 compatible = "allwinner,sun7i-a20-mmc";
559 clocks = <&ccu CLK_AHB_MMC2>,
560 <&ccu CLK_MMC2>,
561 <&ccu CLK_MMC2_OUTPUT>,
562 <&ccu CLK_MMC2_SAMPLE>;
563 clock-names = "ahb",
568 pinctrl-names = "default";
569 pinctrl-0 = <&mmc2_pins>;
571 #address-cells = <1>;
572 #size-cells = <0>;
576 compatible = "allwinner,sun7i-a20-mmc";
578 clocks = <&ccu CLK_AHB_MMC3>,
579 <&ccu CLK_MMC3>,
580 <&ccu CLK_MMC3_OUTPUT>,
581 <&ccu CLK_MMC3_SAMPLE>;
582 clock-names = "ahb",
587 pinctrl-names = "default";
588 pinctrl-0 = <&mmc3_pins>;
590 #address-cells = <1>;
591 #size-cells = <0>;
595 compatible = "allwinner,sun4i-a10-musb";
597 clocks = <&ccu CLK_AHB_OTG>;
599 interrupt-names = "mc";
601 phy-names = "usb";
609 #phy-cells = <1>;
610 compatible = "allwinner,sun7i-a20-usb-phy";
612 reg-names = "phy_ctrl", "pmu1", "pmu2";
613 clocks = <&ccu CLK_USB_PHY>;
614 clock-names = "usb_phy";
615 resets = <&ccu RST_USB_PHY0>,
616 <&ccu RST_USB_PHY1>,
617 <&ccu RST_USB_PHY2>;
618 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
623 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
626 clocks = <&ccu CLK_AHB_EHCI0>;
628 phy-names = "usb";
633 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
636 clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
638 phy-names = "usb";
642 crypto: crypto-engine@1c15000 {
643 compatible = "allwinner,sun7i-a20-crypto",
644 "allwinner,sun4i-a10-crypto";
647 clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
648 clock-names = "ahb", "mod";
652 compatible = "allwinner,sun7i-a20-hdmi",
653 "allwinner,sun5i-a10s-hdmi";
656 clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
657 <&ccu CLK_PLL_VIDEO0_2X>,
658 <&ccu CLK_PLL_VIDEO1_2X>;
659 clock-names = "ahb", "mod", "pll-0", "pll-1";
663 dma-names = "ddc-tx", "ddc-rx", "audio-tx";
667 #address-cells = <1>;
668 #size-cells = <0>;
671 #address-cells = <1>;
672 #size-cells = <0>;
677 remote-endpoint = <&tcon0_out_hdmi>;
682 remote-endpoint = <&tcon1_out_hdmi>;
693 compatible = "allwinner,sun4i-a10-spi";
696 clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
697 clock-names = "ahb", "mod";
700 dma-names = "rx", "tx";
702 #address-cells = <1>;
703 #size-cells = <0>;
704 num-cs = <1>;
708 compatible = "allwinner,sun4i-a10-ahci";
711 clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
716 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
719 clocks = <&ccu CLK_AHB_EHCI1>;
721 phy-names = "usb";
726 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
729 clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
731 phy-names = "usb";
736 compatible = "allwinner,sun7i-a20-csi1",
737 "allwinner,sun4i-a10-csi1";
740 clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>;
741 clock-names = "bus", "ram";
742 resets = <&ccu RST_CSI1>;
747 compatible = "allwinner,sun4i-a10-spi";
750 clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
751 clock-names = "ahb", "mod";
754 dma-names = "rx", "tx";
756 #address-cells = <1>;
757 #size-cells = <0>;
758 num-cs = <1>;
761 ccu: clock@1c20000 { label
762 compatible = "allwinner,sun7i-a20-ccu";
765 clock-names = "hosc", "losc";
766 #clock-cells = <1>;
767 #reset-cells = <1>;
771 compatible = "allwinner,sun7i-a20-pinctrl";
774 clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
775 clock-names = "apb", "hosc", "losc";
776 gpio-controller;
777 interrupt-controller;
778 #interrupt-cells = <3>;
779 #gpio-cells = <3>;
781 /omit-if-no-ref/
782 can_pa_pins: can-pa-pins {
787 /omit-if-no-ref/
788 can_ph_pins: can-ph-pins {
793 /omit-if-no-ref/
794 clk_out_a_pin: clk-out-a-pin {
799 /omit-if-no-ref/
800 clk_out_b_pin: clk-out-b-pin {
805 /omit-if-no-ref/
806 csi0_8bits_pins: csi-8bits-pins {
813 /omit-if-no-ref/
814 csi0_clk_pin: csi-clk-pin {
819 /omit-if-no-ref/
820 csi1_8bits_pg_pins: csi1-8bits-pg-pins {
827 /omit-if-no-ref/
828 csi1_24bits_ph_pins: csi1-24bits-ph-pins {
838 /omit-if-no-ref/
839 csi1_clk_pg_pin: csi1-clk-pg-pin {
844 /omit-if-no-ref/
845 emac_pa_pins: emac-pa-pins {
854 /omit-if-no-ref/
855 emac_ph_pins: emac-ph-pins {
864 /omit-if-no-ref/
865 gmac_mii_pins: gmac-mii-pins {
874 /omit-if-no-ref/
875 gmac_rgmii_pins: gmac-rgmii-pins {
886 drive-strength = <40>;
889 /omit-if-no-ref/
890 i2c0_pins: i2c0-pins {
895 /omit-if-no-ref/
896 i2c1_pins: i2c1-pins {
901 /omit-if-no-ref/
902 i2c2_pins: i2c2-pins {
907 /omit-if-no-ref/
908 i2c3_pins: i2c3-pins {
913 /omit-if-no-ref/
914 ir0_rx_pin: ir0-rx-pin {
919 /omit-if-no-ref/
920 ir0_tx_pin: ir0-tx-pin {
925 /omit-if-no-ref/
926 ir1_rx_pin: ir1-rx-pin {
931 /omit-if-no-ref/
932 ir1_tx_pin: ir1-tx-pin {
937 /omit-if-no-ref/
938 lcd_lvds0_pins: lcd-lvds0-pins {
944 /omit-if-no-ref/
945 lcd_lvds1_pins: lcd-lvds1-pins {
951 /omit-if-no-ref/
952 mmc0_pins: mmc0-pins {
956 drive-strength = <30>;
957 bias-pull-up;
960 /omit-if-no-ref/
961 mmc2_pins: mmc2-pins {
965 drive-strength = <30>;
966 bias-pull-up;
969 /omit-if-no-ref/
970 mmc3_pins: mmc3-pins {
974 drive-strength = <30>;
975 bias-pull-up;
978 /omit-if-no-ref/
979 ps2_0_pins: ps2-0-pins {
984 /omit-if-no-ref/
985 ps2_1_ph_pins: ps2-1-ph-pins {
990 /omit-if-no-ref/
991 pwm0_pin: pwm0-pin {
996 /omit-if-no-ref/
997 pwm1_pin: pwm1-pin {
1002 /omit-if-no-ref/
1003 spdif_tx_pin: spdif-tx-pin {
1006 bias-pull-up;
1009 /omit-if-no-ref/
1010 spi0_pi_pins: spi0-pi-pins {
1015 /omit-if-no-ref/
1016 spi0_cs0_pi_pin: spi0-cs0-pi-pin {
1021 /omit-if-no-ref/
1022 spi0_cs1_pi_pin: spi0-cs1-pi-pin {
1027 /omit-if-no-ref/
1028 spi1_pi_pins: spi1-pi-pins {
1033 /omit-if-no-ref/
1034 spi1_cs0_pi_pin: spi1-cs0-pi-pin {
1039 /omit-if-no-ref/
1040 spi2_pb_pins: spi2-pb-pins {
1045 /omit-if-no-ref/
1046 spi2_cs0_pb_pin: spi2-cs0-pb-pin {
1051 /omit-if-no-ref/
1052 spi2_pc_pins: spi2-pc-pins {
1057 /omit-if-no-ref/
1058 spi2_cs0_pc_pin: spi2-cs0-pc-pin {
1063 /omit-if-no-ref/
1064 uart0_pb_pins: uart0-pb-pins {
1069 /omit-if-no-ref/
1070 uart0_pf_pins: uart0-pf-pins {
1075 /omit-if-no-ref/
1076 uart1_pa_pins: uart1-pa-pins {
1081 /omit-if-no-ref/
1082 uart1_cts_rts_pa_pins: uart1-cts-rts-pa-pins {
1087 /omit-if-no-ref/
1088 uart2_pa_pins: uart2-pa-pins {
1093 /omit-if-no-ref/
1094 uart2_cts_rts_pa_pins: uart2-cts-rts-pa-pins {
1099 /omit-if-no-ref/
1100 uart2_pi_pins: uart2-pi-pins {
1105 /omit-if-no-ref/
1106 uart2_cts_rts_pi_pins: uart2-cts-rts-pi-pins {
1111 /omit-if-no-ref/
1112 uart3_pg_pins: uart3-pg-pins {
1117 /omit-if-no-ref/
1118 uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins {
1123 /omit-if-no-ref/
1124 uart3_ph_pins: uart3-ph-pins {
1129 /omit-if-no-ref/
1130 uart3_cts_rts_ph_pins: uart3-cts-rts-ph-pins {
1135 /omit-if-no-ref/
1136 uart4_pg_pins: uart4-pg-pins {
1141 /omit-if-no-ref/
1142 uart4_ph_pins: uart4-ph-pins {
1147 /omit-if-no-ref/
1148 uart5_ph_pins: uart5-ph-pins {
1153 /omit-if-no-ref/
1154 uart5_pi_pins: uart5-pi-pins {
1159 /omit-if-no-ref/
1160 uart6_pa_pins: uart6-pa-pins {
1165 /omit-if-no-ref/
1166 uart6_pi_pins: uart6-pi-pins {
1171 /omit-if-no-ref/
1172 uart7_pa_pins: uart7-pa-pins {
1177 /omit-if-no-ref/
1178 uart7_pi_pins: uart7-pi-pins {
1185 compatible = "allwinner,sun4i-a10-timer";
1197 compatible = "allwinner,sun4i-a10-wdt";
1204 compatible = "allwinner,sun7i-a20-rtc";
1210 compatible = "allwinner,sun7i-a20-pwm";
1213 #pwm-cells = <3>;
1218 #sound-dai-cells = <0>;
1219 compatible = "allwinner,sun4i-a10-spdif";
1222 clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
1223 clock-names = "apb", "spdif";
1226 dma-names = "rx", "tx";
1231 compatible = "allwinner,sun4i-a10-ir";
1232 clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
1233 clock-names = "apb", "ir";
1240 compatible = "allwinner,sun4i-a10-ir";
1241 clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
1242 clock-names = "apb", "ir";
1249 #sound-dai-cells = <0>;
1250 compatible = "allwinner,sun4i-a10-i2s";
1253 clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>;
1254 clock-names = "apb", "mod";
1257 dma-names = "rx", "tx";
1262 #sound-dai-cells = <0>;
1263 compatible = "allwinner,sun4i-a10-i2s";
1266 clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
1267 clock-names = "apb", "mod";
1270 dma-names = "rx", "tx";
1275 compatible = "allwinner,sun4i-a10-lradc-keys";
1282 #sound-dai-cells = <0>;
1283 compatible = "allwinner,sun7i-a20-codec";
1286 clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
1287 clock-names = "apb", "codec";
1290 dma-names = "rx", "tx";
1295 compatible = "allwinner,sun7i-a20-sid";
1300 #sound-dai-cells = <0>;
1301 compatible = "allwinner,sun4i-a10-i2s";
1304 clocks = <&ccu CLK_APB0_I2S2>, <&ccu CLK_I2S2>;
1305 clock-names = "apb", "mod";
1308 dma-names = "rx", "tx";
1313 compatible = "allwinner,sun5i-a13-ts";
1316 #thermal-sensor-cells = <0>;
1320 compatible = "snps,dw-apb-uart";
1323 reg-shift = <2>;
1324 reg-io-width = <4>;
1325 clocks = <&ccu CLK_APB1_UART0>;
1330 compatible = "snps,dw-apb-uart";
1333 reg-shift = <2>;
1334 reg-io-width = <4>;
1335 clocks = <&ccu CLK_APB1_UART1>;
1340 compatible = "snps,dw-apb-uart";
1343 reg-shift = <2>;
1344 reg-io-width = <4>;
1345 clocks = <&ccu CLK_APB1_UART2>;
1350 compatible = "snps,dw-apb-uart";
1353 reg-shift = <2>;
1354 reg-io-width = <4>;
1355 clocks = <&ccu CLK_APB1_UART3>;
1360 compatible = "snps,dw-apb-uart";
1363 reg-shift = <2>;
1364 reg-io-width = <4>;
1365 clocks = <&ccu CLK_APB1_UART4>;
1370 compatible = "snps,dw-apb-uart";
1373 reg-shift = <2>;
1374 reg-io-width = <4>;
1375 clocks = <&ccu CLK_APB1_UART5>;
1380 compatible = "snps,dw-apb-uart";
1383 reg-shift = <2>;
1384 reg-io-width = <4>;
1385 clocks = <&ccu CLK_APB1_UART6>;
1390 compatible = "snps,dw-apb-uart";
1393 reg-shift = <2>;
1394 reg-io-width = <4>;
1395 clocks = <&ccu CLK_APB1_UART7>;
1400 compatible = "allwinner,sun4i-a10-ps2";
1403 clocks = <&ccu CLK_APB1_PS20>;
1408 compatible = "allwinner,sun4i-a10-ps2";
1411 clocks = <&ccu CLK_APB1_PS21>;
1416 compatible = "allwinner,sun7i-a20-i2c",
1417 "allwinner,sun4i-a10-i2c";
1420 clocks = <&ccu CLK_APB1_I2C0>;
1421 pinctrl-names = "default";
1422 pinctrl-0 = <&i2c0_pins>;
1424 #address-cells = <1>;
1425 #size-cells = <0>;
1429 compatible = "allwinner,sun7i-a20-i2c",
1430 "allwinner,sun4i-a10-i2c";
1433 clocks = <&ccu CLK_APB1_I2C1>;
1434 pinctrl-names = "default";
1435 pinctrl-0 = <&i2c1_pins>;
1437 #address-cells = <1>;
1438 #size-cells = <0>;
1442 compatible = "allwinner,sun7i-a20-i2c",
1443 "allwinner,sun4i-a10-i2c";
1446 clocks = <&ccu CLK_APB1_I2C2>;
1447 pinctrl-names = "default";
1448 pinctrl-0 = <&i2c2_pins>;
1450 #address-cells = <1>;
1451 #size-cells = <0>;
1455 compatible = "allwinner,sun7i-a20-i2c",
1456 "allwinner,sun4i-a10-i2c";
1459 clocks = <&ccu CLK_APB1_I2C3>;
1460 pinctrl-names = "default";
1461 pinctrl-0 = <&i2c3_pins>;
1463 #address-cells = <1>;
1464 #size-cells = <0>;
1468 compatible = "allwinner,sun7i-a20-can",
1469 "allwinner,sun4i-a10-can";
1472 clocks = <&ccu CLK_APB1_CAN>;
1477 compatible = "allwinner,sun7i-a20-i2c",
1478 "allwinner,sun4i-a10-i2c";
1481 clocks = <&ccu CLK_APB1_I2C4>;
1483 #address-cells = <1>;
1484 #size-cells = <0>;
1488 compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
1497 interrupt-names = "gp",
1504 clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
1505 clock-names = "bus", "core";
1506 resets = <&ccu RST_GPU>;
1508 assigned-clocks = <&ccu CLK_GPU>;
1509 assigned-clock-rates = <384000000>;
1513 compatible = "allwinner,sun7i-a20-gmac";
1516 interrupt-names = "macirq";
1517 clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>;
1518 clock-names = "stmmaceth", "allwinner_gmac_tx";
1520 snps,fixed-burst;
1525 compatible = "snps,dwmac-mdio";
1526 #address-cells = <1>;
1527 #size-cells = <0>;
1532 compatible = "allwinner,sun7i-a20-hstimer";
1538 clocks = <&ccu CLK_AHB_HSTIMER>;
1541 gic: interrupt-controller@1c81000 {
1542 compatible = "arm,gic-400";
1547 interrupt-controller;
1548 #interrupt-cells = <3>;
1552 fe0: display-frontend@1e00000 {
1553 compatible = "allwinner,sun7i-a20-display-frontend";
1556 clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
1557 <&ccu CLK_DRAM_DE_FE0>;
1558 clock-names = "ahb", "mod",
1560 resets = <&ccu RST_DE_FE0>;
1563 #address-cells = <1>;
1564 #size-cells = <0>;
1567 #address-cells = <1>;
1568 #size-cells = <0>;
1573 remote-endpoint = <&be0_in_fe0>;
1578 remote-endpoint = <&be1_in_fe0>;
1584 fe1: display-frontend@1e20000 {
1585 compatible = "allwinner,sun7i-a20-display-frontend";
1588 clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
1589 <&ccu CLK_DRAM_DE_FE1>;
1590 clock-names = "ahb", "mod",
1592 resets = <&ccu RST_DE_FE1>;
1595 #address-cells = <1>;
1596 #size-cells = <0>;
1599 #address-cells = <1>;
1600 #size-cells = <0>;
1605 remote-endpoint = <&be0_in_fe1>;
1610 remote-endpoint = <&be1_in_fe1>;
1616 be1: display-backend@1e40000 {
1617 compatible = "allwinner,sun7i-a20-display-backend";
1620 clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
1621 <&ccu CLK_DRAM_DE_BE1>;
1622 clock-names = "ahb", "mod",
1624 resets = <&ccu RST_DE_BE1>;
1627 #address-cells = <1>;
1628 #size-cells = <0>;
1631 #address-cells = <1>;
1632 #size-cells = <0>;
1637 remote-endpoint = <&fe0_out_be1>;
1642 remote-endpoint = <&fe1_out_be1>;
1647 #address-cells = <1>;
1648 #size-cells = <0>;
1653 remote-endpoint = <&tcon0_in_be1>;
1658 remote-endpoint = <&tcon1_in_be1>;
1664 be0: display-backend@1e60000 {
1665 compatible = "allwinner,sun7i-a20-display-backend";
1668 clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
1669 <&ccu CLK_DRAM_DE_BE0>;
1670 clock-names = "ahb", "mod",
1672 resets = <&ccu RST_DE_BE0>;
1675 #address-cells = <1>;
1676 #size-cells = <0>;
1679 #address-cells = <1>;
1680 #size-cells = <0>;
1685 remote-endpoint = <&fe0_out_be0>;
1690 remote-endpoint = <&fe1_out_be0>;
1695 #address-cells = <1>;
1696 #size-cells = <0>;
1701 remote-endpoint = <&tcon0_in_be0>;
1706 remote-endpoint = <&tcon1_in_be0>;