Lines Matching +full:0 +full:x01c50000
101 #size-cells = <0>;
103 cpu0: cpu@0 {
106 reg = <0>;
183 size = <0x6000000>;
184 alloc-ranges = <0x40000000 0x10000000>;
210 #clock-cells = <0>;
217 #clock-cells = <0>;
233 #clock-cells = <0>;
240 #clock-cells = <0>;
247 #clock-cells = <0>;
249 reg = <0x01c20164 0x4>;
271 reg = <0x01c00000 0x30>;
276 sram_a: sram@0 {
278 reg = <0x00000000 0xc000>;
281 ranges = <0 0x00000000 0xc000>;
286 reg = <0x8000 0x4000>;
293 reg = <0x00010000 0x1000>;
296 ranges = <0 0x00010000 0x1000>;
298 otg_sram: sram-section@0 {
301 reg = <0x0000 0x1000>;
308 reg = <0x01d00000 0xd0000>;
311 ranges = <0 0x01d00000 0xd0000>;
313 ve_sram: sram-section@0 {
316 reg = <0x000000 0x80000>;
325 reg = <0x01c00030 0x0c>;
326 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
331 reg = <0x01c02000 0x1000>;
339 reg = <0x01c03000 0x1000>;
347 #size-cells = <0>;
352 reg = <0x01c05000 0x1000>;
361 #size-cells = <0>;
367 reg = <0x01c06000 0x1000>;
376 #size-cells = <0>;
382 reg = <0x01c09000 0x1000>;
392 reg = <0x01c0b000 0x1000>;
401 reg = <0x01c0b080 0x14>;
404 #size-cells = <0>;
410 reg = <0x01c0c000 0x1000>;
421 #clock-cells = <0>;
426 #size-cells = <0>;
428 tcon0_in: port@0 {
430 #size-cells = <0>;
431 reg = <0>;
433 tcon0_in_be0: endpoint@0 {
434 reg = <0>;
446 #size-cells = <0>;
461 reg = <0x01c0d000 0x1000>;
472 #clock-cells = <0>;
477 #size-cells = <0>;
479 tcon1_in: port@0 {
481 #size-cells = <0>;
482 reg = <0>;
484 tcon1_in_be0: endpoint@0 {
485 reg = <0>;
497 #size-cells = <0>;
511 reg = <0x01c0e000 0x1000>;
522 reg = <0x01c0f000 0x1000>;
533 pinctrl-0 = <&mmc0_pins>;
536 #size-cells = <0>;
541 reg = <0x01c10000 0x1000>;
553 #size-cells = <0>;
558 reg = <0x01c11000 0x1000>;
569 pinctrl-0 = <&mmc2_pins>;
572 #size-cells = <0>;
577 reg = <0x01c12000 0x1000>;
588 pinctrl-0 = <&mmc3_pins>;
591 #size-cells = <0>;
596 reg = <0x01c13000 0x0400>;
600 phys = <&usbphy 0>;
602 extcon = <&usbphy 0>;
611 reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;
624 reg = <0x01c14000 0x100>;
634 reg = <0x01c14400 0x100>;
645 reg = <0x01c15000 0x1000>;
654 reg = <0x01c16000 0x1000>;
659 clock-names = "ahb", "mod", "pll-0", "pll-1";
668 #size-cells = <0>;
670 hdmi_in: port@0 {
672 #size-cells = <0>;
673 reg = <0>;
675 hdmi_in_tcon0: endpoint@0 {
676 reg = <0>;
694 reg = <0x01c17000 0x1000>;
703 #size-cells = <0>;
709 reg = <0x01c18000 0x1000>;
717 reg = <0x01c1c000 0x100>;
727 reg = <0x01c1c400 0x100>;
738 reg = <0x01c1d000 0x1000>;
748 reg = <0x01c1f000 0x1000>;
757 #size-cells = <0>;
763 reg = <0x01c20000 0x400>;
772 reg = <0x01c20800 0x400>;
979 ps2_0_pins: ps2-0-pins {
1186 reg = <0x01c20c00 0x90>;
1198 reg = <0x01c20c90 0x10>;
1205 reg = <0x01c20d00 0x20>;
1211 reg = <0x01c20e00 0xc>;
1218 #sound-dai-cells = <0>;
1220 reg = <0x01c21000 0x400>;
1235 reg = <0x01c21800 0x40>;
1244 reg = <0x01c21c00 0x40>;
1249 #sound-dai-cells = <0>;
1251 reg = <0x01c22000 0x400>;
1262 #sound-dai-cells = <0>;
1264 reg = <0x01c22400 0x400>;
1276 reg = <0x01c22800 0x100>;
1282 #sound-dai-cells = <0>;
1284 reg = <0x01c22c00 0x40>;
1296 reg = <0x01c23800 0x200>;
1300 #sound-dai-cells = <0>;
1302 reg = <0x01c24400 0x400>;
1314 reg = <0x01c25000 0x100>;
1316 #thermal-sensor-cells = <0>;
1321 reg = <0x01c28000 0x400>;
1331 reg = <0x01c28400 0x400>;
1341 reg = <0x01c28800 0x400>;
1351 reg = <0x01c28c00 0x400>;
1361 reg = <0x01c29000 0x400>;
1371 reg = <0x01c29400 0x400>;
1381 reg = <0x01c29800 0x400>;
1391 reg = <0x01c29c00 0x400>;
1401 reg = <0x01c2a000 0x400>;
1409 reg = <0x01c2a400 0x400>;
1418 reg = <0x01c2ac00 0x400>;
1422 pinctrl-0 = <&i2c0_pins>;
1425 #size-cells = <0>;
1431 reg = <0x01c2b000 0x400>;
1435 pinctrl-0 = <&i2c1_pins>;
1438 #size-cells = <0>;
1444 reg = <0x01c2b400 0x400>;
1448 pinctrl-0 = <&i2c2_pins>;
1451 #size-cells = <0>;
1457 reg = <0x01c2b800 0x400>;
1461 pinctrl-0 = <&i2c3_pins>;
1464 #size-cells = <0>;
1470 reg = <0x01c2bc00 0x400>;
1479 reg = <0x01c2c000 0x400>;
1484 #size-cells = <0>;
1489 reg = <0x01c40000 0x10000>;
1514 reg = <0x01c50000 0x10000>;
1527 #size-cells = <0>;
1533 reg = <0x01c60000 0x1000>;
1543 reg = <0x01c81000 0x1000>,
1544 <0x01c82000 0x2000>,
1545 <0x01c84000 0x2000>,
1546 <0x01c86000 0x2000>;
1554 reg = <0x01e00000 0x20000>;
1564 #size-cells = <0>;
1568 #size-cells = <0>;
1571 fe0_out_be0: endpoint@0 {
1572 reg = <0>;
1586 reg = <0x01e20000 0x20000>;
1596 #size-cells = <0>;
1600 #size-cells = <0>;
1603 fe1_out_be0: endpoint@0 {
1604 reg = <0>;
1618 reg = <0x01e40000 0x10000>;
1628 #size-cells = <0>;
1630 be1_in: port@0 {
1632 #size-cells = <0>;
1633 reg = <0>;
1635 be1_in_fe0: endpoint@0 {
1636 reg = <0>;
1648 #size-cells = <0>;
1651 be1_out_tcon0: endpoint@0 {
1652 reg = <0>;
1666 reg = <0x01e60000 0x10000>;
1676 #size-cells = <0>;
1678 be0_in: port@0 {
1680 #size-cells = <0>;
1681 reg = <0>;
1683 be0_in_fe0: endpoint@0 {
1684 reg = <0>;
1696 #size-cells = <0>;
1699 be0_out_tcon0: endpoint@0 {
1700 reg = <0>;