Lines Matching +full:0 +full:x01c25000
100 #size-cells = <0>;
102 cpu0: cpu@0 {
105 reg = <0>;
216 #clock-cells = <0>;
224 #clock-cells = <0>;
241 #clock-cells = <0>;
248 #clock-cells = <0>;
255 #clock-cells = <0>;
257 reg = <0x01c200d0 0x4>;
277 reg = <0x01c02000 0x1000>;
286 reg = <0x01c0c000 0x1000>;
302 #clock-cells = <0>;
306 #size-cells = <0>;
308 tcon0_in: port@0 {
310 #size-cells = <0>;
311 reg = <0>;
313 tcon0_in_drc0: endpoint@0 {
314 reg = <0>;
326 #size-cells = <0>;
340 reg = <0x01c0d000 0x1000>;
355 #clock-cells = <0>;
359 #size-cells = <0>;
361 tcon1_in: port@0 {
363 #size-cells = <0>;
364 reg = <0>;
366 tcon1_in_drc0: endpoint@0 {
367 reg = <0>;
379 #size-cells = <0>;
393 reg = <0x01c0f000 0x1000>;
406 pinctrl-0 = <&mmc0_pins>;
409 #size-cells = <0>;
414 reg = <0x01c10000 0x1000>;
427 pinctrl-0 = <&mmc1_pins>;
430 #size-cells = <0>;
435 reg = <0x01c11000 0x1000>;
449 #size-cells = <0>;
454 reg = <0x01c12000 0x1000>;
468 #size-cells = <0>;
473 reg = <0x01c16000 0x1000>;
479 clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1";
487 #size-cells = <0>;
489 hdmi_in: port@0 {
491 #size-cells = <0>;
492 reg = <0>;
494 hdmi_in_tcon0: endpoint@0 {
495 reg = <0>;
513 reg = <0x01c19000 0x0400>;
518 phys = <&usbphy 0>;
520 extcon = <&usbphy 0>;
527 reg = <0x01c19400 0x10>,
528 <0x01c1a800 0x4>,
529 <0x01c1b800 0x4>;
551 reg = <0x01c1a000 0x100>;
562 reg = <0x01c1a400 0x100>;
573 reg = <0x01c1b000 0x100>;
584 reg = <0x01c1b400 0x100>;
595 reg = <0x01c1c400 0x100>;
604 reg = <0x01c20000 0x400>;
605 clocks = <&osc24M>, <&rtc 0>;
613 reg = <0x01c20800 0x400>;
618 clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&rtc 0>;
746 reg = <0x01c20c00 0xa0>;
758 reg = <0x01c20ca0 0x20>;
764 #sound-dai-cells = <0>;
766 reg = <0x01c21000 0x400>;
777 #sound-dai-cells = <0>;
779 reg = <0x01c22000 0x400>;
790 #sound-dai-cells = <0>;
792 reg = <0x01c22400 0x400>;
804 reg = <0x01c22800 0x100>;
811 reg = <0x01c25000 0x100>;
813 #thermal-sensor-cells = <0>;
818 reg = <0x01c28000 0x400>;
819 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
831 reg = <0x01c28400 0x400>;
844 reg = <0x01c28800 0x400>;
857 reg = <0x01c28c00 0x400>;
870 reg = <0x01c29000 0x400>;
883 reg = <0x01c29400 0x400>;
896 reg = <0x01c2ac00 0x400>;
901 pinctrl-0 = <&i2c0_pins>;
904 #size-cells = <0>;
909 reg = <0x01c2b000 0x400>;
914 pinctrl-0 = <&i2c1_pins>;
917 #size-cells = <0>;
922 reg = <0x01c2b400 0x400>;
927 pinctrl-0 = <&i2c2_pins>;
930 #size-cells = <0>;
935 reg = <0x01c2b800 0x400>;
941 #size-cells = <0>;
946 reg = <0x01c30000 0x1054>;
961 #size-cells = <0>;
968 reg = <0x01c15000 0x1000>;
977 #sound-dai-cells = <0>;
979 reg = <0x01c22c00 0x400>;
992 reg = <0x01c60000 0x1000>;
1003 reg = <0x01c68000 0x1000>;
1012 #size-cells = <0>;
1017 reg = <0x01c69000 0x1000>;
1026 #size-cells = <0>;
1031 reg = <0x01c6a000 0x1000>;
1040 #size-cells = <0>;
1045 reg = <0x01c6b000 0x1000>;
1054 #size-cells = <0>;
1059 reg = <0x01c81000 0x1000>,
1060 <0x01c82000 0x2000>,
1061 <0x01c84000 0x2000>,
1062 <0x01c86000 0x2000>;
1070 reg = <0x01e00000 0x20000>;
1080 #size-cells = <0>;
1084 #size-cells = <0>;
1087 fe0_out_be0: endpoint@0 {
1088 reg = <0>;
1102 reg = <0x01e20000 0x20000>;
1112 #size-cells = <0>;
1116 #size-cells = <0>;
1119 fe1_out_be0: endpoint@0 {
1120 reg = <0>;
1134 reg = <0x01e40000 0x10000>;
1144 #size-cells = <0>;
1146 be1_in: port@0 {
1148 #size-cells = <0>;
1149 reg = <0>;
1151 be1_in_fe0: endpoint@0 {
1152 reg = <0>;
1164 #size-cells = <0>;
1177 reg = <0x01e50000 0x10000>;
1187 #size-cells = <0>;
1189 drc1_in: port@0 {
1191 #size-cells = <0>;
1192 reg = <0>;
1202 #size-cells = <0>;
1205 drc1_out_tcon0: endpoint@0 {
1206 reg = <0>;
1220 reg = <0x01e60000 0x10000>;
1230 #size-cells = <0>;
1232 be0_in: port@0 {
1234 #size-cells = <0>;
1235 reg = <0>;
1237 be0_in_fe0: endpoint@0 {
1238 reg = <0>;
1260 reg = <0x01e70000 0x10000>;
1270 #size-cells = <0>;
1272 drc0_in: port@0 {
1273 reg = <0>;
1282 #size-cells = <0>;
1285 drc0_out_tcon0: endpoint@0 {
1286 reg = <0>;
1301 reg = <0x01f00000 0x54>;
1312 reg = <0x01f00c00 0x400>;
1318 reg = <0x01f01400 0x200>;
1322 #clock-cells = <0>;
1323 clocks = <&rtc 0>, <&osc24M>,
1331 #clock-cells = <0>;
1340 #clock-cells = <0>;
1356 #clock-cells = <0>;
1358 clocks = <&rtc 0>, <&osc24M>;
1370 reg = <0x01f01c00 0x300>;
1379 reg = <0x01f02000 0x40>;
1385 reg = <0x01f02c00 0x400>;
1388 clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
1390 resets = <&apb0_rst 0>;
1409 reg = <0x01f03400 0x400>;
1415 pinctrl-0 = <&s_p2wi_pins>;
1418 #size-cells = <0>;