Lines Matching +full:1 +full:c0b000
50 #address-cells = <1>;
51 #size-cells = <1>;
59 #address-cells = <1>;
60 #size-cells = <1>;
110 #address-cells = <1>;
162 #address-cells = <1>;
163 #size-cells = <1>;
193 #address-cells = <1>;
194 #size-cells = <1>;
209 #address-cells = <1>;
210 #size-cells = <1>;
213 system-control@1c00000 {
216 #address-cells = <1>;
217 #size-cells = <1>;
223 #address-cells = <1>;
224 #size-cells = <1>;
237 #address-cells = <1>;
238 #size-cells = <1>;
248 sram_c: sram@1d00000 {
251 #address-cells = <1>;
252 #size-cells = <1>;
262 dma: dma-controller@1c02000 {
270 nfc: nand-controller@1c03000 {
279 #address-cells = <1>;
283 spi0: spi@1c05000 {
293 #address-cells = <1>;
297 spi1: spi@1c06000 {
309 #address-cells = <1>;
313 emac: ethernet@1c0b000 {
318 allwinner,sram = <&emac_sram 1>;
324 mdio: mdio@1c0b080 {
328 #address-cells = <1>;
332 tcon0: lcd-controller@1c0c000 {
349 #address-cells = <1>;
353 #address-cells = <1>;
362 tcon0_in_be1: endpoint@1 {
363 reg = <1>;
368 tcon0_out: port@1 {
369 #address-cells = <1>;
371 reg = <1>;
373 tcon0_out_hdmi: endpoint@1 {
374 reg = <1>;
376 allwinner,tcon-channel = <1>;
382 tcon1: lcd-controller@1c0d000 {
399 #address-cells = <1>;
403 #address-cells = <1>;
412 tcon1_in_be1: endpoint@1 {
413 reg = <1>;
418 tcon1_out: port@1 {
419 #address-cells = <1>;
421 reg = <1>;
423 tcon1_out_hdmi: endpoint@1 {
424 reg = <1>;
426 allwinner,tcon-channel = <1>;
432 video-codec@1c0e000 {
440 allwinner,sram = <&ve_sram 1>;
443 mmc0: mmc@1c0f000 {
452 #address-cells = <1>;
456 mmc1: mmc@1c10000 {
463 #address-cells = <1>;
467 mmc2: mmc@1c11000 {
474 #address-cells = <1>;
478 mmc3: mmc@1c12000 {
485 #address-cells = <1>;
489 usb_otg: usb@1c13000 {
498 allwinner,sram = <&otg_sram 1>;
503 usbphy: phy@1c13400 {
504 #phy-cells = <1>;
517 ehci0: usb@1c14000 {
522 phys = <&usbphy 1>;
527 ohci0: usb@1c14400 {
532 phys = <&usbphy 1>;
537 crypto: crypto-engine@1c15000 {
545 hdmi: hdmi@1c16000 {
552 clock-names = "ahb", "mod", "pll-0", "pll-1";
560 #address-cells = <1>;
564 #address-cells = <1>;
573 hdmi_in_tcon1: endpoint@1 {
574 reg = <1>;
579 hdmi_out: port@1 {
580 reg = <1>;
585 spi2: spi@1c17000 {
595 #address-cells = <1>;
599 ahci: sata@1c18000 {
607 ehci1: usb@1c1c000 {
617 ohci1: usb@1c1c400 {
627 csi1: csi@1c1d000 {
637 spi3: spi@1c1f000 {
647 #address-cells = <1>;
651 ccu: clock@1c20000 {
656 #clock-cells = <1>;
657 #reset-cells = <1>;
660 intc: interrupt-controller@1c20400 {
664 #interrupt-cells = <1>;
667 pio: pinctrl@1c20800 {
842 timer@1c20c00 {
854 wdt: watchdog@1c20c90 {
861 rtc: rtc@1c20d00 {
867 pwm: pwm@1c20e00 {
875 spdif: spdif@1c21000 {
888 ir0: ir@1c21800 {
897 ir1: ir@1c21c00 {
906 i2s0: i2s@1c22400 {
919 lradc: lradc@1c22800 {
926 codec: codec@1c22c00 {
939 sid: eeprom@1c23800 {
944 rtp: rtp@1c25000 {
951 uart0: serial@1c28000 {
954 interrupts = <1>;
961 uart1: serial@1c28400 {
971 uart2: serial@1c28800 {
981 uart3: serial@1c28c00 {
991 uart4: serial@1c29000 {
1001 uart5: serial@1c29400 {
1011 uart6: serial@1c29800 {
1021 uart7: serial@1c29c00 {
1031 ps20: ps2@1c2a000 {
1039 ps21: ps2@1c2a400 {
1047 i2c0: i2c@1c2ac00 {
1055 #address-cells = <1>;
1059 i2c1: i2c@1c2b000 {
1067 #address-cells = <1>;
1071 i2c2: i2c@1c2b400 {
1079 #address-cells = <1>;
1083 can0: can@1c2bc00 {
1091 mali: gpu@1c40000 {
1112 fe0: display-frontend@1e00000 {
1123 #address-cells = <1>;
1126 fe0_out: port@1 {
1127 #address-cells = <1>;
1129 reg = <1>;
1136 fe0_out_be1: endpoint@1 {
1137 reg = <1>;
1144 fe1: display-frontend@1e20000 {
1155 #address-cells = <1>;
1158 fe1_out: port@1 {
1159 #address-cells = <1>;
1161 reg = <1>;
1168 fe1_out_be1: endpoint@1 {
1169 reg = <1>;
1176 be1: display-backend@1e40000 {
1187 #address-cells = <1>;
1191 #address-cells = <1>;
1200 be1_in_fe1: endpoint@1 {
1201 reg = <1>;
1206 be1_out: port@1 {
1207 #address-cells = <1>;
1209 reg = <1>;
1216 be1_out_tcon1: endpoint@1 {
1217 reg = <1>;
1224 be0: display-backend@1e60000 {
1235 #address-cells = <1>;
1239 #address-cells = <1>;
1248 be0_in_fe1: endpoint@1 {
1249 reg = <1>;
1254 be0_out: port@1 {
1255 #address-cells = <1>;
1257 reg = <1>;
1264 be0_out_tcon1: endpoint@1 {
1265 reg = <1>;