Lines Matching +full:1 +full:- +full:9 +full:a +full:- +full:f
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
9 adc1_in6_pins_a: adc1-in6-0 {
11 pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
15 adc12_ain_pins_a: adc12-ain-0 {
18 <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
19 <STM32_PINMUX('F', 13, ANALOG)>, /* ADC2 in2 */
20 <STM32_PINMUX('F', 14, ANALOG)>; /* ADC2 in6 */
24 adc12_ain_pins_b: adc12-ain-1 {
26 pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
27 <STM32_PINMUX('F', 13, ANALOG)>; /* ADC2 in2 */
31 adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 {
33 pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */
34 <STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */
38 cec_pins_a: cec-0 {
40 pinmux = <STM32_PINMUX('A', 15, AF4)>;
41 bias-disable;
42 drive-open-drain;
43 slew-rate = <0>;
47 cec_sleep_pins_a: cec-sleep-0 {
49 pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */
53 cec_pins_b: cec-1 {
56 bias-disable;
57 drive-open-drain;
58 slew-rate = <0>;
62 cec_sleep_pins_b: cec-sleep-1 {
68 dac_ch1_pins_a: dac-ch1-0 {
70 pinmux = <STM32_PINMUX('A', 4, ANALOG)>;
74 dac_ch2_pins_a: dac-ch2-0 {
76 pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
80 dcmi_pins_a: dcmi-0 {
84 <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
85 <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */
93 <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
97 bias-disable;
101 dcmi_sleep_pins_a: dcmi-sleep-0 {
105 <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
106 <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */
114 <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
121 ethernet0_rgmii_pins_a: rgmii-0 {
130 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
131 bias-disable;
132 drive-push-pull;
133 slew-rate = <2>;
136 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
137 bias-disable;
138 drive-push-pull;
139 slew-rate = <0>;
145 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
146 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
147 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
148 bias-disable;
152 ethernet0_rgmii_sleep_pins_a: rgmii-sleep-0 {
161 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
162 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
166 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
167 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
168 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
172 ethernet0_rgmii_pins_b: rgmii-1 {
181 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
182 bias-disable;
183 drive-push-pull;
184 slew-rate = <2>;
187 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
188 bias-disable;
189 drive-push-pull;
190 slew-rate = <0>;
197 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
198 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
199 bias-disable;
203 ethernet0_rgmii_sleep_pins_b: rgmii-sleep-1 {
212 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
213 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
218 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
219 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
223 ethernet0_rgmii_pins_c: rgmii-2 {
232 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
233 bias-disable;
234 drive-push-pull;
235 slew-rate = <2>;
238 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
239 bias-disable;
240 drive-push-pull;
241 slew-rate = <0>;
247 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
248 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
249 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
250 bias-disable;
254 ethernet0_rgmii_sleep_pins_c: rgmii-sleep-2 {
263 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
264 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
268 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
269 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
270 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
274 ethernet0_rmii_pins_a: rmii-0 {
279 <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */
280 <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
281 <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
282 bias-disable;
283 drive-push-pull;
284 slew-rate = <2>;
289 <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
290 bias-disable;
294 ethernet0_rmii_sleep_pins_a: rmii-sleep-0 {
299 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
300 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
303 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
304 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
308 fmc_pins_a: fmc-0 {
317 <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
320 <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
322 <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */
323 bias-disable;
324 drive-push-pull;
325 slew-rate = <1>;
329 bias-pull-up;
333 fmc_sleep_pins_a: fmc-sleep-0 {
342 <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
345 <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
348 <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */
352 i2c1_pins_a: i2c1-0 {
355 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
356 bias-disable;
357 drive-open-drain;
358 slew-rate = <0>;
362 i2c1_sleep_pins_a: i2c1-sleep-0 {
365 <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
369 i2c1_pins_b: i2c1-1 {
371 pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */
372 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
373 bias-disable;
374 drive-open-drain;
375 slew-rate = <0>;
379 i2c1_sleep_pins_b: i2c1-sleep-1 {
381 pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */
382 <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
386 i2c2_pins_a: i2c2-0 {
390 bias-disable;
391 drive-open-drain;
392 slew-rate = <0>;
396 i2c2_sleep_pins_a: i2c2-sleep-0 {
403 i2c2_pins_b1: i2c2-1 {
406 bias-disable;
407 drive-open-drain;
408 slew-rate = <0>;
412 i2c2_sleep_pins_b1: i2c2-sleep-1 {
418 i2c2_pins_c: i2c2-2 {
420 pinmux = <STM32_PINMUX('F', 1, AF4)>, /* I2C2_SCL */
422 bias-disable;
423 drive-open-drain;
424 slew-rate = <0>;
428 i2c2_pins_sleep_c: i2c2-sleep-2 {
430 pinmux = <STM32_PINMUX('F', 1, ANALOG)>, /* I2C2_SCL */
435 i2c5_pins_a: i2c5-0 {
437 pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
438 <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
439 bias-disable;
440 drive-open-drain;
441 slew-rate = <0>;
445 i2c5_sleep_pins_a: i2c5-sleep-0 {
447 pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */
448 <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */
453 i2c5_pins_b: i2c5-1 {
456 <STM32_PINMUX('D', 1, AF4)>; /* I2C5_SDA */
457 bias-disable;
458 drive-open-drain;
459 slew-rate = <0>;
463 i2c5_sleep_pins_b: i2c5-sleep-1 {
466 <STM32_PINMUX('D', 1, ANALOG)>; /* I2C5_SDA */
470 i2s2_pins_a: i2s2-0 {
473 <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */
474 <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */
475 slew-rate = <1>;
476 drive-push-pull;
477 bias-disable;
481 i2s2_sleep_pins_a: i2s2-sleep-0 {
484 <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */
485 <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */
489 ltdc_pins_a: ltdc-0 {
493 <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
494 <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */
498 <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
509 <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */
511 <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
516 <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */
519 bias-disable;
520 drive-push-pull;
521 slew-rate = <1>;
525 ltdc_sleep_pins_a: ltdc-sleep-0 {
529 <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
530 <STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */
534 <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
545 <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */
547 <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
552 <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */
558 ltdc_pins_b: ltdc-1 {
566 <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
574 <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
578 <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
588 bias-disable;
589 drive-push-pull;
590 slew-rate = <1>;
594 ltdc_sleep_pins_b: ltdc-sleep-1 {
602 <STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */
610 <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */
614 <STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */
627 ltdc_pins_c: ltdc-2 {
629 pinmux = <STM32_PINMUX('B', 1, AF9)>, /* LTDC_R6 */
630 <STM32_PINMUX('B', 9, AF14)>, /* LTDC_B7 */
641 <STM32_PINMUX('H', 9, AF14)>, /* LTDC_R3 */
645 <STM32_PINMUX('I', 1, AF14)>, /* LTDC_G6 */
648 <STM32_PINMUX('I', 9, AF14)>, /* LTDC_VSYNC */
650 bias-disable;
651 drive-push-pull;
652 slew-rate = <0>;
656 bias-disable;
657 drive-push-pull;
658 slew-rate = <1>;
662 ltdc_sleep_pins_c: ltdc-sleep-2 {
664 pinmux = <STM32_PINMUX('B', 1, ANALOG)>, /* LTDC_R6 */
665 <STM32_PINMUX('B', 9, ANALOG)>, /* LTDC_B7 */
676 <STM32_PINMUX('H', 9, ANALOG)>, /* LTDC_R3 */
680 <STM32_PINMUX('I', 1, ANALOG)>, /* LTDC_G6 */
683 <STM32_PINMUX('I', 9, ANALOG)>, /* LTDC_VSYNC */
689 ltdc_pins_d: ltdc-3 {
692 bias-disable;
693 drive-push-pull;
694 slew-rate = <3>;
698 <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
703 <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
704 <STM32_PINMUX('A', 5, AF14)>, /* LCD_R4 */
716 <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
721 <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */
724 bias-disable;
725 drive-push-pull;
726 slew-rate = <2>;
730 ltdc_sleep_pins_d: ltdc-sleep-3 {
734 <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
739 <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
740 <STM32_PINMUX('A', 5, ANALOG)>, /* LCD_R4 */
752 <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
757 <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */
763 m_can1_pins_a: m-can1-0 {
766 slew-rate = <1>;
767 drive-push-pull;
768 bias-disable;
771 pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */
772 bias-disable;
776 m_can1_sleep_pins_a: m_can1-sleep-0 {
779 <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */
783 m_can1_pins_b: m-can1-1 {
785 pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */
786 slew-rate = <1>;
787 drive-push-pull;
788 bias-disable;
791 pinmux = <STM32_PINMUX('A', 11, AF9)>; /* CAN1_RX */
792 bias-disable;
796 m_can1_sleep_pins_b: m_can1-sleep-1 {
798 pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* CAN1_TX */
799 <STM32_PINMUX('A', 11, ANALOG)>; /* CAN1_RX */
803 m_can2_pins_a: m-can2-0 {
806 slew-rate = <1>;
807 drive-push-pull;
808 bias-disable;
812 bias-disable;
816 m_can2_sleep_pins_a: m_can2-sleep-0 {
823 pwm1_pins_a: pwm1-0 {
825 pinmux = <STM32_PINMUX('E', 9, AF1)>, /* TIM1_CH1 */
828 bias-pull-down;
829 drive-push-pull;
830 slew-rate = <0>;
834 pwm1_sleep_pins_a: pwm1-sleep-0 {
836 pinmux = <STM32_PINMUX('E', 9, ANALOG)>, /* TIM1_CH1 */
842 pwm2_pins_a: pwm2-0 {
844 pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
845 bias-pull-down;
846 drive-push-pull;
847 slew-rate = <0>;
851 pwm2_sleep_pins_a: pwm2-sleep-0 {
853 pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* TIM2_CH4 */
857 pwm3_pins_a: pwm3-0 {
860 bias-pull-down;
861 drive-push-pull;
862 slew-rate = <0>;
866 pwm3_sleep_pins_a: pwm3-sleep-0 {
872 pwm3_pins_b: pwm3-1 {
875 bias-disable;
876 drive-push-pull;
877 slew-rate = <0>;
881 pwm3_sleep_pins_b: pwm3-sleep-1 {
887 pwm4_pins_a: pwm4-0 {
891 bias-pull-down;
892 drive-push-pull;
893 slew-rate = <0>;
897 pwm4_sleep_pins_a: pwm4-sleep-0 {
904 pwm4_pins_b: pwm4-1 {
907 bias-pull-down;
908 drive-push-pull;
909 slew-rate = <0>;
913 pwm4_sleep_pins_b: pwm4-sleep-1 {
919 pwm5_pins_a: pwm5-0 {
922 bias-pull-down;
923 drive-push-pull;
924 slew-rate = <0>;
928 pwm5_sleep_pins_a: pwm5-sleep-0 {
934 pwm5_pins_b: pwm5-1 {
939 bias-disable;
940 drive-push-pull;
941 slew-rate = <0>;
945 pwm5_sleep_pins_b: pwm5-sleep-1 {
953 pwm8_pins_a: pwm8-0 {
956 bias-pull-down;
957 drive-push-pull;
958 slew-rate = <0>;
962 pwm8_sleep_pins_a: pwm8-sleep-0 {
968 pwm12_pins_a: pwm12-0 {
971 bias-pull-down;
972 drive-push-pull;
973 slew-rate = <0>;
977 pwm12_sleep_pins_a: pwm12-sleep-0 {
983 qspi_clk_pins_a: qspi-clk-0 {
985 pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
986 bias-disable;
987 drive-push-pull;
988 slew-rate = <3>;
992 qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
994 pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
998 qspi_bk1_pins_a: qspi-bk1-0 {
1000 pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
1001 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
1002 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
1003 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
1004 bias-disable;
1005 drive-push-pull;
1006 slew-rate = <1>;
1010 bias-pull-up;
1011 drive-push-pull;
1012 slew-rate = <1>;
1016 qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
1018 pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
1019 <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
1020 <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
1021 <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */
1026 qspi_bk2_pins_a: qspi-bk2-0 {
1032 bias-disable;
1033 drive-push-pull;
1034 slew-rate = <1>;
1038 bias-pull-up;
1039 drive-push-pull;
1040 slew-rate = <1>;
1044 qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
1054 sai2a_pins_a: sai2a-0 {
1060 slew-rate = <0>;
1061 drive-push-pull;
1062 bias-disable;
1066 sai2a_sleep_pins_a: sai2a-sleep-0 {
1075 sai2a_pins_b: sai2a-1 {
1080 slew-rate = <0>;
1081 drive-push-pull;
1082 bias-disable;
1086 sai2a_sleep_pins_b: sai2a-sleep-1 {
1094 sai2a_pins_c: sai2a-4 {
1099 slew-rate = <0>;
1100 drive-push-pull;
1101 bias-disable;
1105 sai2a_sleep_pins_c: sai2a-5 {
1113 sai2b_pins_a: sai2b-0 {
1118 slew-rate = <0>;
1119 drive-push-pull;
1120 bias-disable;
1123 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
1124 bias-disable;
1128 sai2b_sleep_pins_a: sai2b-sleep-0 {
1130 pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */
1137 sai2b_pins_b: sai2b-1 {
1139 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
1140 bias-disable;
1144 sai2b_sleep_pins_b: sai2b-sleep-1 {
1146 pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
1150 sai2b_pins_c: sai2a-4 {
1152 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
1153 bias-disable;
1157 sai2b_sleep_pins_c: sai2a-sleep-5 {
1159 pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
1163 sai4a_pins_a: sai4a-0 {
1166 slew-rate = <0>;
1167 drive-push-pull;
1168 bias-disable;
1172 sai4a_sleep_pins_a: sai4a-sleep-0 {
1178 sdmmc1_b4_pins_a: sdmmc1-b4-0 {
1181 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
1185 slew-rate = <1>;
1186 drive-push-pull;
1187 bias-disable;
1191 slew-rate = <2>;
1192 drive-push-pull;
1193 bias-disable;
1197 sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
1200 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
1203 slew-rate = <1>;
1204 drive-push-pull;
1205 bias-disable;
1209 slew-rate = <2>;
1210 drive-push-pull;
1211 bias-disable;
1215 slew-rate = <1>;
1216 drive-open-drain;
1217 bias-disable;
1221 sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
1224 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
1232 sdmmc1_dir_pins_a: sdmmc1-dir-0 {
1234 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
1236 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
1237 slew-rate = <1>;
1238 drive-push-pull;
1239 bias-pull-up;
1243 bias-pull-up;
1247 sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
1249 pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
1251 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
1256 sdmmc1_dir_pins_b: sdmmc1-dir-1 {
1258 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
1260 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
1261 slew-rate = <1>;
1262 drive-push-pull;
1263 bias-pull-up;
1267 bias-pull-up;
1271 sdmmc1_dir_sleep_pins_b: sdmmc1-dir-sleep-1 {
1273 pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
1275 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
1280 sdmmc2_b4_pins_a: sdmmc2-b4-0 {
1287 slew-rate = <1>;
1288 drive-push-pull;
1289 bias-pull-up;
1293 slew-rate = <2>;
1294 drive-push-pull;
1295 bias-pull-up;
1299 sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
1305 slew-rate = <1>;
1306 drive-push-pull;
1307 bias-pull-up;
1311 slew-rate = <2>;
1312 drive-push-pull;
1313 bias-pull-up;
1317 slew-rate = <1>;
1318 drive-open-drain;
1319 bias-pull-up;
1323 sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
1334 sdmmc2_b4_pins_b: sdmmc2-b4-1 {
1341 slew-rate = <1>;
1342 drive-push-pull;
1343 bias-disable;
1347 slew-rate = <2>;
1348 drive-push-pull;
1349 bias-disable;
1353 sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 {
1359 slew-rate = <1>;
1360 drive-push-pull;
1361 bias-disable;
1365 slew-rate = <2>;
1366 drive-push-pull;
1367 bias-disable;
1371 slew-rate = <1>;
1372 drive-open-drain;
1373 bias-disable;
1377 sdmmc2_d47_pins_a: sdmmc2-d47-0 {
1379 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
1380 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
1383 slew-rate = <1>;
1384 drive-push-pull;
1385 bias-pull-up;
1389 sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
1391 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
1392 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
1398 sdmmc2_d47_pins_b: sdmmc2-d47-1 {
1400 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
1401 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
1404 slew-rate = <1>;
1405 drive-push-pull;
1406 bias-disable;
1410 sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 {
1412 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
1413 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
1419 sdmmc2_d47_pins_c: sdmmc2-d47-2 {
1421 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
1422 <STM32_PINMUX('A', 15, AF9)>, /* SDMMC2_D5 */
1425 slew-rate = <1>;
1426 drive-push-pull;
1427 bias-pull-up;
1431 sdmmc2_d47_sleep_pins_c: sdmmc2-d47-sleep-2 {
1433 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
1434 <STM32_PINMUX('A', 15, ANALOG)>, /* SDMMC2_D5 */
1440 sdmmc2_d47_pins_d: sdmmc2-d47-3 {
1442 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
1443 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
1449 sdmmc2_d47_sleep_pins_d: sdmmc2-d47-sleep-3 {
1451 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
1452 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
1458 sdmmc3_b4_pins_a: sdmmc3-b4-0 {
1460 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
1461 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
1462 <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
1464 <STM32_PINMUX('F', 1, AF9)>; /* SDMMC3_CMD */
1465 slew-rate = <1>;
1466 drive-push-pull;
1467 bias-pull-up;
1471 slew-rate = <2>;
1472 drive-push-pull;
1473 bias-pull-up;
1477 sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 {
1479 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
1480 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
1481 <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
1483 slew-rate = <1>;
1484 drive-push-pull;
1485 bias-pull-up;
1489 slew-rate = <2>;
1490 drive-push-pull;
1491 bias-pull-up;
1494 pinmux = <STM32_PINMUX('F', 1, AF9)>; /* SDMMC2_CMD */
1495 slew-rate = <1>;
1496 drive-open-drain;
1497 bias-pull-up;
1501 sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 {
1503 pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */
1504 <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */
1505 <STM32_PINMUX('F', 5, ANALOG)>, /* SDMMC3_D2 */
1508 <STM32_PINMUX('F', 1, ANALOG)>; /* SDMMC3_CMD */
1512 sdmmc3_b4_pins_b: sdmmc3-b4-1 {
1514 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
1515 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
1519 slew-rate = <1>;
1520 drive-push-pull;
1521 bias-pull-up;
1525 slew-rate = <2>;
1526 drive-push-pull;
1527 bias-pull-up;
1531 sdmmc3_b4_od_pins_b: sdmmc3-b4-od-1 {
1533 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
1534 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
1537 slew-rate = <1>;
1538 drive-push-pull;
1539 bias-pull-up;
1543 slew-rate = <2>;
1544 drive-push-pull;
1545 bias-pull-up;
1549 slew-rate = <1>;
1550 drive-open-drain;
1551 bias-pull-up;
1555 sdmmc3_b4_sleep_pins_b: sdmmc3-b4-sleep-1 {
1557 pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */
1558 <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */
1566 spdifrx_pins_a: spdifrx-0 {
1569 bias-disable;
1573 spdifrx_sleep_pins_a: spdifrx-sleep-0 {
1579 spi2_pins_a: spi2-0 {
1583 bias-disable;
1584 drive-push-pull;
1585 slew-rate = <1>;
1590 bias-disable;
1594 uart4_pins_a: uart4-0 {
1597 bias-disable;
1598 drive-push-pull;
1599 slew-rate = <0>;
1603 bias-disable;
1607 uart4_idle_pins_a: uart4-idle-0 {
1613 bias-disable;
1617 uart4_sleep_pins_a: uart4-sleep-0 {
1624 uart4_pins_b: uart4-1 {
1626 pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
1627 bias-disable;
1628 drive-push-pull;
1629 slew-rate = <0>;
1633 bias-disable;
1637 uart4_pins_c: uart4-2 {
1640 bias-disable;
1641 drive-push-pull;
1642 slew-rate = <0>;
1646 bias-disable;
1650 uart7_pins_a: uart7-0 {
1653 bias-disable;
1654 drive-push-pull;
1655 slew-rate = <0>;
1660 <STM32_PINMUX('E', 9, AF7)>; /* UART7_RTS */
1661 bias-disable;
1665 uart7_pins_b: uart7-1 {
1667 pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */
1668 bias-disable;
1669 drive-push-pull;
1670 slew-rate = <0>;
1673 pinmux = <STM32_PINMUX('F', 6, AF7)>; /* UART7_RX */
1674 bias-disable;
1678 uart7_pins_c: uart7-2 {
1681 bias-disable;
1682 drive-push-pull;
1683 slew-rate = <0>;
1687 bias-disable;
1691 uart7_idle_pins_c: uart7-idle-2 {
1697 bias-disable;
1701 uart7_sleep_pins_c: uart7-sleep-2 {
1708 uart8_pins_a: uart8-0 {
1710 pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
1711 bias-disable;
1712 drive-push-pull;
1713 slew-rate = <0>;
1717 bias-disable;
1721 uart8_rtscts_pins_a: uart8rtscts-0 {
1725 bias-disable;
1729 spi4_pins_a: spi4-0 {
1733 bias-disable;
1734 drive-push-pull;
1735 slew-rate = <1>;
1739 bias-disable;
1743 usart2_pins_a: usart2-0 {
1745 pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
1747 bias-disable;
1748 drive-push-pull;
1749 slew-rate = <0>;
1754 bias-disable;
1758 usart2_sleep_pins_a: usart2-sleep-0 {
1760 pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */
1767 usart2_pins_b: usart2-1 {
1769 pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
1770 <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */
1771 bias-disable;
1772 drive-push-pull;
1773 slew-rate = <0>;
1776 pinmux = <STM32_PINMUX('F', 4, AF7)>, /* USART2_RX */
1778 bias-disable;
1782 usart2_sleep_pins_b: usart2-sleep-1 {
1784 pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */
1785 <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */
1786 <STM32_PINMUX('F', 4, ANALOG)>, /* USART2_RX */
1791 usart2_pins_c: usart2-2 {
1795 bias-disable;
1796 drive-push-pull;
1797 slew-rate = <3>;
1802 bias-disable;
1806 usart2_idle_pins_c: usart2-idle-2 {
1814 bias-disable;
1818 usart2_sleep_pins_c: usart2-sleep-2 {
1827 usart3_pins_a: usart3-0 {
1830 bias-disable;
1831 drive-push-pull;
1832 slew-rate = <0>;
1836 bias-disable;
1840 usart3_pins_b: usart3-1 {
1844 bias-disable;
1845 drive-push-pull;
1846 slew-rate = <0>;
1851 bias-disable;
1855 usart3_idle_pins_b: usart3-idle-1 {
1863 bias-disable;
1867 usart3_sleep_pins_b: usart3-sleep-1 {
1876 usart3_pins_c: usart3-2 {
1880 bias-disable;
1881 drive-push-pull;
1882 slew-rate = <0>;
1887 bias-disable;
1891 usart3_idle_pins_c: usart3-idle-2 {
1899 bias-disable;
1903 usart3_sleep_pins_c: usart3-sleep-2 {
1912 usbotg_hs_pins_a: usbotg-hs-0 {
1914 pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
1918 usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 {
1920 pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */
1921 <STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */
1927 i2c2_pins_b2: i2c2-0 {
1930 bias-disable;
1931 drive-open-drain;
1932 slew-rate = <0>;
1936 i2c2_sleep_pins_b2: i2c2-sleep-0 {
1942 i2c4_pins_a: i2c4-0 {
1946 bias-disable;
1947 drive-open-drain;
1948 slew-rate = <0>;
1952 i2c4_sleep_pins_a: i2c4-sleep-0 {
1959 spi1_pins_a: spi1-0 {
1963 bias-disable;
1964 drive-push-pull;
1965 slew-rate = <1>;
1969 pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */
1970 bias-disable;