Lines Matching +full:no +full:- +full:pbl +full:- +full:x8
2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
4 * This file is dual-licensed: you can use it either under the terms
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 #include "armv7-m.dtsi"
44 #include <dt-bindings/clock/stm32h7-clks.h>
45 #include <dt-bindings/mfd/stm32h7-rcc.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
49 #address-cells = <1>;
50 #size-cells = <1>;
53 clk_hse: clk-hse {
54 #clock-cells = <0>;
55 compatible = "fixed-clock";
56 clock-frequency = <0>;
59 clk_lse: clk-lse {
60 #clock-cells = <0>;
61 compatible = "fixed-clock";
62 clock-frequency = <32768>;
66 #clock-cells = <0>;
67 compatible = "fixed-clock";
68 clock-frequency = <0>;
74 compatible = "st,stm32-timer";
81 #address-cells = <1>;
82 #size-cells = <0>;
83 compatible = "st,stm32-lptimer";
86 clock-names = "mux";
90 compatible = "st,stm32-pwm-lp";
91 #pwm-cells = <3>;
96 compatible = "st,stm32-lptimer-trigger";
102 compatible = "st,stm32-lptimer-counter";
108 #address-cells = <1>;
109 #size-cells = <0>;
110 compatible = "st,stm32h7-spi";
120 #address-cells = <1>;
121 #size-cells = <0>;
122 compatible = "st,stm32h7-spi";
131 compatible = "st,stm32h7-uart";
139 compatible = "st,stm32f7-i2c";
140 #address-cells = <1>;
141 #size-cells = <0>;
151 compatible = "st,stm32f7-i2c";
152 #address-cells = <1>;
153 #size-cells = <0>;
163 compatible = "st,stm32f7-i2c";
164 #address-cells = <1>;
165 #size-cells = <0>;
175 compatible = "st,stm32h7-dac-core";
178 clock-names = "pclk";
179 #address-cells = <1>;
180 #size-cells = <0>;
184 compatible = "st,stm32-dac";
185 #io-channel-cells = <1>;
191 compatible = "st,stm32-dac";
192 #io-channel-cells = <1>;
199 compatible = "st,stm32h7-uart";
207 #address-cells = <1>;
208 #size-cells = <0>;
209 compatible = "st,stm32h7-spi";
218 #address-cells = <1>;
219 #size-cells = <0>;
220 compatible = "st,stm32h7-spi";
229 #address-cells = <1>;
230 #size-cells = <0>;
231 compatible = "st,stm32h7-spi";
239 dma1: dma-controller@40020000 {
240 compatible = "st,stm32-dma";
251 #dma-cells = <4>;
253 dma-requests = <8>;
257 dma2: dma-controller@40020400 {
258 compatible = "st,stm32-dma";
269 #dma-cells = <4>;
271 dma-requests = <8>;
275 dmamux1: dma-router@40020800 {
276 compatible = "st,stm32h7-dmamux";
278 #dma-cells = <3>;
279 dma-channels = <16>;
280 dma-requests = <128>;
281 dma-masters = <&dma1 &dma2>;
286 compatible = "st,stm32h7-adc-core";
290 clock-names = "bus";
291 interrupt-controller;
292 #interrupt-cells = <1>;
293 #address-cells = <1>;
294 #size-cells = <0>;
298 compatible = "st,stm32h7-adc";
299 #io-channel-cells = <1>;
301 interrupt-parent = <&adc_12>;
307 compatible = "st,stm32h7-adc";
308 #io-channel-cells = <1>;
310 interrupt-parent = <&adc_12>;
317 compatible = "st,stm32f7-hsotg";
321 clock-names = "otg";
322 g-rx-fifo-size = <256>;
323 g-np-tx-fifo-size = <32>;
324 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
329 compatible = "st,stm32f4x9-fsotg";
333 clock-names = "otg";
337 ltdc: display-controller@50001000 {
338 compatible = "st,stm32-ltdc";
343 clock-names = "lcd";
347 mdma1: dma-controller@52000000 {
348 compatible = "st,stm32h7-mdma";
352 #dma-cells = <5>;
353 dma-channels = <16>;
354 dma-requests = <32>;
359 arm,primecell-periphid = <0x10153180>;
362 interrupt-names = "cmd_irq";
364 clock-names = "apb_pclk";
366 cap-sd-highspeed;
367 cap-mmc-highspeed;
368 max-frequency = <120000000>;
371 exti: interrupt-controller@58000000 {
372 compatible = "st,stm32h7-exti";
373 interrupt-controller;
374 #interrupt-cells = <2>;
380 compatible = "st,stm32-syscfg", "syscon";
385 #address-cells = <1>;
386 #size-cells = <0>;
387 compatible = "st,stm32h7-spi";
396 compatible = "st,stm32f7-i2c";
397 #address-cells = <1>;
398 #size-cells = <0>;
408 #address-cells = <1>;
409 #size-cells = <0>;
410 compatible = "st,stm32-lptimer";
413 clock-names = "mux";
417 compatible = "st,stm32-pwm-lp";
418 #pwm-cells = <3>;
423 compatible = "st,stm32-lptimer-trigger";
429 compatible = "st,stm32-lptimer-counter";
435 #address-cells = <1>;
436 #size-cells = <0>;
437 compatible = "st,stm32-lptimer";
440 clock-names = "mux";
444 compatible = "st,stm32-pwm-lp";
445 #pwm-cells = <3>;
450 compatible = "st,stm32-lptimer-trigger";
457 #address-cells = <1>;
458 #size-cells = <0>;
459 compatible = "st,stm32-lptimer";
462 clock-names = "mux";
466 compatible = "st,stm32-pwm-lp";
467 #pwm-cells = <3>;
473 #address-cells = <1>;
474 #size-cells = <0>;
475 compatible = "st,stm32-lptimer";
478 clock-names = "mux";
482 compatible = "st,stm32-pwm-lp";
483 #pwm-cells = <3>;
489 compatible = "st,stm32-vrefbuf";
490 reg = <0x58003C00 0x8>;
492 regulator-min-microvolt = <1500000>;
493 regulator-max-microvolt = <2500000>;
498 compatible = "st,stm32h7-rtc";
501 clock-names = "pclk", "rtc_ck";
502 assigned-clocks = <&rcc RTC_CK>;
503 assigned-clock-parents = <&rcc LSE_CK>;
504 interrupt-parent = <&exti>;
510 rcc: reset-clock-controller@58024400 {
511 compatible = "st,stm32h743-rcc", "st,stm32-rcc";
513 #clock-cells = <1>;
514 #reset-cells = <1>;
519 pwrcfg: power-config@58024800 {
520 compatible = "st,stm32-power-config", "syscon";
525 compatible = "st,stm32h7-adc-core";
529 clock-names = "bus";
530 interrupt-controller;
531 #interrupt-cells = <1>;
532 #address-cells = <1>;
533 #size-cells = <0>;
537 compatible = "st,stm32h7-adc";
538 #io-channel-cells = <1>;
540 interrupt-parent = <&adc_3>;
547 compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
549 reg-names = "stmmaceth";
551 interrupt-names = "macirq";
552 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
555 snps,pbl = <8>;
562 clock-frequency = <250000000>;