Lines Matching +full:mixed +full:- +full:burst
2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
22 * MA 02110-1301 USA
48 #include "armv7-m.dtsi"
49 #include <dt-bindings/clock/stm32fx-clock.h>
50 #include <dt-bindings/mfd/stm32f4-rcc.h>
53 #address-cells = <1>;
54 #size-cells = <1>;
57 clk_hse: clk-hse {
58 #clock-cells = <0>;
59 compatible = "fixed-clock";
60 clock-frequency = <0>;
63 clk_lse: clk-lse {
64 #clock-cells = <0>;
65 compatible = "fixed-clock";
66 clock-frequency = <32768>;
69 clk_lsi: clk-lsi {
70 #clock-cells = <0>;
71 compatible = "fixed-clock";
72 clock-frequency = <32000>;
75 clk_i2s_ckin: i2s-ckin {
76 #clock-cells = <0>;
77 compatible = "fixed-clock";
78 clock-frequency = <0>;
84 compatible = "st,stm32f4-otp";
86 #address-cells = <1>;
87 #size-cells = <1>;
97 compatible = "st,stm32-timer";
105 #address-cells = <1>;
106 #size-cells = <0>;
107 compatible = "st,stm32-timers";
110 clock-names = "int";
114 compatible = "st,stm32-pwm";
115 #pwm-cells = <3>;
120 compatible = "st,stm32-timer-trigger";
127 compatible = "st,stm32-timer";
135 #address-cells = <1>;
136 #size-cells = <0>;
137 compatible = "st,stm32-timers";
140 clock-names = "int";
144 compatible = "st,stm32-pwm";
145 #pwm-cells = <3>;
150 compatible = "st,stm32-timer-trigger";
157 compatible = "st,stm32-timer";
165 #address-cells = <1>;
166 #size-cells = <0>;
167 compatible = "st,stm32-timers";
170 clock-names = "int";
174 compatible = "st,stm32-pwm";
175 #pwm-cells = <3>;
180 compatible = "st,stm32-timer-trigger";
187 compatible = "st,stm32-timer";
194 #address-cells = <1>;
195 #size-cells = <0>;
196 compatible = "st,stm32-timers";
199 clock-names = "int";
203 compatible = "st,stm32-pwm";
204 #pwm-cells = <3>;
209 compatible = "st,stm32-timer-trigger";
216 compatible = "st,stm32-timer";
224 #address-cells = <1>;
225 #size-cells = <0>;
226 compatible = "st,stm32-timers";
229 clock-names = "int";
233 compatible = "st,stm32-timer-trigger";
240 compatible = "st,stm32-timer";
248 #address-cells = <1>;
249 #size-cells = <0>;
250 compatible = "st,stm32-timers";
253 clock-names = "int";
257 compatible = "st,stm32-timer-trigger";
264 #address-cells = <1>;
265 #size-cells = <0>;
266 compatible = "st,stm32-timers";
269 clock-names = "int";
273 compatible = "st,stm32-pwm";
274 #pwm-cells = <3>;
279 compatible = "st,stm32-timer-trigger";
286 #address-cells = <1>;
287 #size-cells = <0>;
288 compatible = "st,stm32-timers";
291 clock-names = "int";
295 compatible = "st,stm32-pwm";
296 #pwm-cells = <3>;
302 #address-cells = <1>;
303 #size-cells = <0>;
304 compatible = "st,stm32-timers";
307 clock-names = "int";
311 compatible = "st,stm32-pwm";
312 #pwm-cells = <3>;
318 compatible = "st,stm32-rtc";
321 assigned-clocks = <&rcc 1 CLK_RTC>;
322 assigned-clock-parents = <&rcc 1 CLK_LSE>;
323 interrupt-parent = <&exti>;
330 compatible = "st,stm32-iwdg";
333 clock-names = "lsi";
338 #address-cells = <1>;
339 #size-cells = <0>;
340 compatible = "st,stm32f4-spi";
348 #address-cells = <1>;
349 #size-cells = <0>;
350 compatible = "st,stm32f4-spi";
358 compatible = "st,stm32-uart";
366 compatible = "st,stm32-uart";
373 dma-names = "rx", "tx";
377 compatible = "st,stm32-uart";
385 compatible = "st,stm32-uart";
393 compatible = "st,stm32f4-i2c";
399 #address-cells = <1>;
400 #size-cells = <0>;
405 compatible = "st,stm32f4-i2c";
411 #address-cells = <1>;
412 #size-cells = <0>;
417 compatible = "st,stm32f4-dac-core";
421 clock-names = "pclk";
422 #address-cells = <1>;
423 #size-cells = <0>;
427 compatible = "st,stm32-dac";
428 #io-channel-cells = <1>;
434 compatible = "st,stm32-dac";
435 #io-channel-cells = <1>;
442 compatible = "st,stm32-uart";
450 compatible = "st,stm32-uart";
458 #address-cells = <1>;
459 #size-cells = <0>;
460 compatible = "st,stm32-timers";
463 clock-names = "int";
467 compatible = "st,stm32-pwm";
468 #pwm-cells = <3>;
473 compatible = "st,stm32-timer-trigger";
480 #address-cells = <1>;
481 #size-cells = <0>;
482 compatible = "st,stm32-timers";
485 clock-names = "int";
489 compatible = "st,stm32-pwm";
490 #pwm-cells = <3>;
495 compatible = "st,stm32-timer-trigger";
502 compatible = "st,stm32-uart";
509 dma-names = "rx", "tx";
513 compatible = "st,stm32-uart";
521 compatible = "st,stm32f4-adc-core";
525 clock-names = "adc";
526 interrupt-controller;
527 #interrupt-cells = <1>;
528 #address-cells = <1>;
529 #size-cells = <0>;
533 compatible = "st,stm32f4-adc";
534 #io-channel-cells = <1>;
537 interrupt-parent = <&adc>;
540 dma-names = "rx";
545 compatible = "st,stm32f4-adc";
546 #io-channel-cells = <1>;
549 interrupt-parent = <&adc>;
552 dma-names = "rx";
557 compatible = "st,stm32f4-adc";
558 #io-channel-cells = <1>;
561 interrupt-parent = <&adc>;
564 dma-names = "rx";
571 arm,primecell-periphid = <0x00880180>;
574 clock-names = "apb_pclk";
576 max-frequency = <48000000>;
581 #address-cells = <1>;
582 #size-cells = <0>;
583 compatible = "st,stm32f4-spi";
591 #address-cells = <1>;
592 #size-cells = <0>;
593 compatible = "st,stm32f4-spi";
601 compatible = "st,stm32-syscfg", "syscon";
605 exti: interrupt-controller@40013c00 {
606 compatible = "st,stm32-exti";
607 interrupt-controller;
608 #interrupt-cells = <2>;
614 #address-cells = <1>;
615 #size-cells = <0>;
616 compatible = "st,stm32-timers";
619 clock-names = "int";
623 compatible = "st,stm32-pwm";
624 #pwm-cells = <3>;
629 compatible = "st,stm32-timer-trigger";
636 #address-cells = <1>;
637 #size-cells = <0>;
638 compatible = "st,stm32-timers";
641 clock-names = "int";
645 compatible = "st,stm32-pwm";
646 #pwm-cells = <3>;
652 #address-cells = <1>;
653 #size-cells = <0>;
654 compatible = "st,stm32-timers";
657 clock-names = "int";
661 compatible = "st,stm32-pwm";
662 #pwm-cells = <3>;
668 #address-cells = <1>;
669 #size-cells = <0>;
670 compatible = "st,stm32f4-spi";
676 dma-names = "rx", "tx";
681 #address-cells = <1>;
682 #size-cells = <0>;
683 compatible = "st,stm32f4-spi";
690 pwrcfg: power-config@40007000 {
691 compatible = "st,stm32-power-config", "syscon";
695 ltdc: display-controller@40016800 {
696 compatible = "st,stm32-ltdc";
701 clock-names = "lcd";
706 compatible = "st,stm32f4-crc";
713 #reset-cells = <1>;
714 #clock-cells = <2>;
715 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
719 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
720 assigned-clock-rates = <1000000>;
723 dma1: dma-controller@40026000 {
724 compatible = "st,stm32-dma";
735 #dma-cells = <4>;
738 dma2: dma-controller@40026400 {
739 compatible = "st,stm32-dma";
750 #dma-cells = <4>;
755 compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
757 reg-names = "stmmaceth";
759 interrupt-names = "macirq";
760 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
766 snps,mixed-burst;
775 clock-names = "otg";
780 compatible = "st,stm32f4x9-fsotg";
784 clock-names = "otg";
789 compatible = "st,stm32-dcmi";
794 clock-names = "mclk";
795 pinctrl-names = "default";
796 pinctrl-0 = <&dcmi_pins>;
798 dma-names = "tx";
803 compatible = "st,stm32-rng";