Lines Matching +full:1 +full:e40000
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <1>;
34 #address-cells = <1>;
56 cpu@1 {
59 reg = <1>;
119 #address-cells = <1>;
120 #size-cells = <1>;
135 #reset-cells = <1>;
141 #reset-cells = <1>;
147 #reset-cells = <1>;
181 #sound-dai-cells = <1>;
279 #address-cells = <1>;
294 #address-cells = <1>;
309 #address-cells = <1>;
324 #address-cells = <1>;
339 #address-cells = <1>;
354 #address-cells = <1>;
371 #address-cells = <1>;
386 #address-cells = <1>;
405 #address-cells = <1>;
406 #size-cells = <1>;
419 #phy-cells = <1>;
435 #phy-cells = <1>;
449 #phy-cells = <1>;
464 #address-cells = <1>;
478 #address-cells = <1>;
492 #address-cells = <1>;
506 #address-cells = <1>;
520 #address-cells = <1>;
535 #address-cells = <1>;
549 #address-cells = <1>;
563 #address-cells = <1>;
676 #address-cells = <1>;
677 #size-cells = <1>;
706 st,pwm-num-chan = <1>;
773 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
812 #mbox-cells = <1>;
814 mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>;
826 #mbox-cells = <1>;
828 mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>;
849 fdma1: dma-controller@8e40000 {
897 dmas = <&fdma0 2 0 1>;
908 assigned-clocks = <&clk_s_d0_quadfs 1>, <&clk_s_d0_flexgen CLK_PCM_1>;
909 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>;
913 dmas = <&fdma0 3 0 1>;
929 dmas = <&fdma0 4 0 1>;
945 dmas = <&fdma0 7 0 1>;
957 dmas = <&fdma0 5 0 1>;
969 dmas = <&fdma0 6 0 1>;