Lines Matching +full:0 +full:xa0351000
38 #size-cells = <0>;
54 reg = <0x300>;
63 reg = <0x301>;
79 polling-delay = <0>;
91 hysteresis = <0>;
113 reg = <0x801ae000 0x1000>;
129 reg = <0x801af000 0x1000>;
145 reg = <0x801a6000 0x1000>;
160 #size-cells = <0>;
162 port@0 {
163 reg = <0>;
185 #size-cells = <0>;
187 port@0 {
188 reg = <0>;
212 reg = <0x80190000 0x1000>;
227 reg = <0x801a4000 0x1000>;
245 reg = <0xa0411000 0x1000>,
246 <0xa0410100 0x100>;
251 reg = <0xa0410000 0x100>;
260 reg = <0x80150000 0x2000>;
265 reg = <0xa0412000 0x1000>;
287 reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
288 <0x8000f000 0x1000>, <0xa03ff000 0x1000>,
289 <0xa03cf000 0x1000>;
304 #clock-cells = <0>;
308 #clock-cells = <0>;
315 reg = <0xa03c6000 0x1000>;
324 reg = <0xa0410600 0x20>;
332 reg = <0xa0410620 0x20>;
339 reg = <0x80154000 0x1000>;
349 reg = <0x8012e000 0x80>;
356 gpio-bank = <0>;
357 gpio-ranges = <&pinctrl 0 0 32>;
364 reg = <0x8012e080 0x80>;
372 gpio-ranges = <&pinctrl 0 32 5>;
379 reg = <0x8000e000 0x80>;
387 gpio-ranges = <&pinctrl 0 64 32>;
394 reg = <0x8000e080 0x80>;
402 gpio-ranges = <&pinctrl 0 96 2>;
409 reg = <0x8000e100 0x80>;
417 gpio-ranges = <&pinctrl 0 128 32>;
424 reg = <0x8000e180 0x80>;
432 gpio-ranges = <&pinctrl 0 160 12>;
439 reg = <0x8011e000 0x80>;
447 gpio-ranges = <&pinctrl 0 192 32>;
454 reg = <0x8011e080 0x80>;
462 gpio-ranges = <&pinctrl 0 224 7>;
469 reg = <0xa03fe000 0x80>;
477 gpio-ranges = <&pinctrl 0 256 12>;
491 reg = <0xa03e0000 0x10000>;
497 dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
498 <&dma 38 0 0x0>, /* Logical - MemToDev */
499 <&dma 37 0 0x2>, /* Logical - DevToMem */
500 <&dma 37 0 0x0>, /* Logical - MemToDev */
501 <&dma 36 0 0x2>, /* Logical - DevToMem */
502 <&dma 36 0 0x0>, /* Logical - MemToDev */
503 <&dma 19 0 0x2>, /* Logical - DevToMem */
504 <&dma 19 0 0x0>, /* Logical - MemToDev */
505 <&dma 18 0 0x2>, /* Logical - DevToMem */
506 <&dma 18 0 0x0>, /* Logical - MemToDev */
507 <&dma 17 0 0x2>, /* Logical - DevToMem */
508 <&dma 17 0 0x0>, /* Logical - MemToDev */
509 <&dma 16 0 0x2>, /* Logical - DevToMem */
510 <&dma 16 0 0x0>, /* Logical - MemToDev */
511 <&dma 39 0 0x2>, /* Logical - DevToMem */
512 <&dma 39 0 0x0>; /* Logical - MemToDev */
523 clocks = <&prcc_pclk 5 0>;
528 reg = <0x801C0000 0x1000 0x40010000 0x800>;
540 reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
551 reg = <0x80157450 0xC>;
556 reg = <0x801573c0 0x40>;
561 #thermal-sensor-cells = <0>;
654 reg = <0x80004000 0x1000>;
658 #size-cells = <0>;
671 reg = <0x80122000 0x1000>;
675 #size-cells = <0>;
689 reg = <0x80128000 0x1000>;
693 #size-cells = <0>;
707 reg = <0x80110000 0x1000>;
711 #size-cells = <0>;
716 clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>;
725 reg = <0x8012a000 0x1000>;
729 #size-cells = <0>;
743 reg = <0x80002000 0x1000>;
746 #size-cells = <0>;
749 dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
750 <&dma 8 0 0x0>; /* Logical - MemToDev */
759 reg = <0x80003000 0x1000>;
762 #size-cells = <0>;
765 dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
766 <&dma 9 0 0x0>; /* Logical - MemToDev */
775 reg = <0x8011a000 0x1000>;
778 #size-cells = <0>;
782 dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
783 <&dma 0 0 0x0>; /* Logical - MemToDev */
792 reg = <0x80112000 0x1000>;
795 #size-cells = <0>;
799 dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
800 <&dma 35 0 0x0>; /* Logical - MemToDev */
809 reg = <0x80111000 0x1000>;
812 #size-cells = <0>;
816 dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
817 <&dma 33 0 0x0>; /* Logical - MemToDev */
826 reg = <0x80129000 0x1000>;
829 #size-cells = <0>;
833 dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
834 <&dma 40 0 0x0>; /* Logical - MemToDev */
843 reg = <0x80120000 0x1000>;
846 dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
847 <&dma 13 0 0x0>; /* Logical - MemToDev */
850 clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>;
858 reg = <0x80121000 0x1000>;
861 dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
862 <&dma 12 0 0x0>; /* Logical - MemToDev */
873 reg = <0x80007000 0x1000>;
876 dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
877 <&dma 11 0 0x0>; /* Logical - MemToDev */
888 reg = <0x80126000 0x1000>;
891 dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
892 <&dma 29 0 0x0>; /* Logical - MemToDev */
904 reg = <0x80118000 0x1000>;
907 dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
908 <&dma 32 0 0x0>; /* Logical - MemToDev */
920 reg = <0x80005000 0x1000>;
923 dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
924 <&dma 28 0 0x0>; /* Logical - MemToDev */
936 reg = <0x80119000 0x1000>;
939 dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */
940 <&dma 41 0 0x0>; /* Logical - MemToDev */
952 reg = <0x80114000 0x1000>;
955 dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
956 <&dma 42 0 0x0>; /* Logical - MemToDev */
968 reg = <0x80008000 0x1000>;
971 dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */
972 <&dma 43 0 0x0>; /* Logical - MemToDev */
989 reg = <0x80123000 0x1000>;
993 dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */
994 <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */
1005 reg = <0x80124000 0x1000>;
1010 dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */
1022 reg = <0x80117000 0x1000>;
1026 dmas = <&dma 14 0 0x12>, /* Logical - DevToMem - HighPrio */
1027 <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev
1039 reg = <0x80125000 0x1000>;
1044 dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */
1055 reg = <0x50000000 0x4000000>;
1058 ranges = <0 0x50000000 0x4000000>;
1069 reg = <0xa0300000 0x10000>;
1088 reg = <0xa0350000 0x1000>;
1102 reg = <0xa0351000 0x1000>;
1106 #size-cells = <0>;
1110 reg = <0xa0352000 0x1000>;
1114 #size-cells = <0>;
1118 reg = <0xa0353000 0x1000>;
1123 #size-cells = <0>;
1129 reg = <0xa03cb000 0x1000>;
1138 reg = <0xa03c2000 0x1000>;