Lines Matching +full:0 +full:xffd04000
15 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
36 reg = <0xffffd000 0x1000>,
37 <0xffffc100 0x100>;
56 reg = <0xffda1000 0x1000>;
57 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
58 <0 84 IRQ_TYPE_LEVEL_HIGH>,
59 <0 85 IRQ_TYPE_LEVEL_HIGH>,
60 <0 86 IRQ_TYPE_LEVEL_HIGH>,
61 <0 87 IRQ_TYPE_LEVEL_HIGH>,
62 <0 88 IRQ_TYPE_LEVEL_HIGH>,
63 <0 89 IRQ_TYPE_LEVEL_HIGH>,
64 <0 90 IRQ_TYPE_LEVEL_HIGH>,
65 <0 91 IRQ_TYPE_LEVEL_HIGH>;
77 #address-cells = <0x1>;
78 #size-cells = <0x1>;
86 reg = <0xffd04000 0x1000>;
90 #size-cells = <0>;
93 #clock-cells = <0>;
98 #clock-cells = <0>;
103 #clock-cells = <0>;
108 #clock-cells = <0>;
114 #size-cells = <0>;
115 #clock-cells = <0>;
119 reg = <0x40>;
122 #clock-cells = <0>;
125 div-reg = <0x140 0 11>;
129 #clock-cells = <0>;
132 div-reg = <0x144 0 11>;
136 #clock-cells = <0>;
139 reg = <0x68>;
143 #clock-cells = <0>;
146 reg = <0x6C>;
150 #clock-cells = <0>;
153 reg = <0x70>;
157 #clock-cells = <0>;
160 reg = <0x74>;
164 #clock-cells = <0>;
168 reg = <0x78>;
172 #clock-cells = <0>;
175 reg = <0x7C>;
179 #clock-cells = <0>;
182 reg = <0x80>;
186 #clock-cells = <0>;
189 reg = <0x84>;
193 #clock-cells = <0>;
196 reg = <0x9C>;
202 #size-cells = <0>;
203 #clock-cells = <0>;
207 reg = <0xC0>;
210 #clock-cells = <0>;
213 div-reg = <0x140 16 11>;
217 #clock-cells = <0>;
220 div-reg = <0x144 16 11>;
224 #clock-cells = <0>;
227 reg = <0xE8>;
231 #clock-cells = <0>;
234 reg = <0xEC>;
238 #clock-cells = <0>;
241 reg = <0xF0>;
245 #clock-cells = <0>;
248 reg = <0xF4>;
252 #clock-cells = <0>;
255 reg = <0xF8>;
259 #clock-cells = <0>;
262 reg = <0xFC>;
266 #clock-cells = <0>;
269 reg = <0x100>;
273 #clock-cells = <0>;
276 reg = <0x104>;
281 #clock-cells = <0>;
286 reg = <0x60>;
290 #clock-cells = <0>;
295 reg = <0x64>;
299 #clock-cells = <0>;
304 reg = <0x104>;
308 #clock-cells = <0>;
314 reg = <0xF8>;
318 #clock-cells = <0>;
325 #clock-cells = <0>;
328 div-reg = <0xA8 0 2>;
329 clk-gate = <0x48 1>;
333 #clock-cells = <0>;
336 div-reg = <0xA8 8 2>;
337 clk-gate = <0x48 2>;
341 #clock-cells = <0>;
344 div-reg = <0xA8 16 2>;
345 clk-gate = <0x48 3>;
349 #clock-cells = <0>;
353 clk-gate = <0x48 0>;
357 #clock-cells = <0>;
360 clk-gate = <0xC8 5>;
361 clk-phase = <0 135>;
365 #clock-cells = <0>;
368 clk-gate = <0xC8 11>;
372 #clock-cells = <0>;
375 clk-gate = <0xC8 10>;
379 #clock-cells = <0>;
382 clk-gate = <0xC8 10>;
386 #clock-cells = <0>;
390 clk-gate = <0xC8 10>;
394 #clock-cells = <0>;
397 clk-gate = <0xC8 9>;
401 #clock-cells = <0>;
404 clk-gate = <0xC8 8>;
408 #clock-cells = <0>;
411 clk-gate = <0xC8 6>;
417 snps,wr_osr_lmt = <0xf>;
418 snps,rd_osr_lmt = <0xf>;
419 snps,blen = <0 0 0 0 16 0 0>;
424 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
425 reg = <0xff800000 0x2000>;
426 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
444 altr,sysmgr-syscon = <&sysmgr 0x48 8>;
445 reg = <0xff802000 0x2000>;
446 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
464 altr,sysmgr-syscon = <&sysmgr 0x4C 16>;
465 reg = <0xff804000 0x2000>;
466 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
484 #size-cells = <0>;
486 reg = <0xffc02900 0x100>;
490 porta: gpio-controller@0 {
495 reg = <0>;
498 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
504 #size-cells = <0>;
506 reg = <0xffc02a00 0x100>;
510 portb: gpio-controller@0 {
515 reg = <0>;
518 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
524 #size-cells = <0>;
526 reg = <0xffc02b00 0x100>;
530 portc: gpio-controller@0 {
535 reg = <0>;
538 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
544 reg = <0xffd03000 0x100
545 0xffcfe400 0x20>;
553 #size-cells = <0>;
555 reg = <0xffc02200 0x100>;
556 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
564 #size-cells = <0>;
566 reg = <0xffc02300 0x100>;
567 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
575 #size-cells = <0>;
577 reg = <0xffc02400 0x100>;
578 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
586 #size-cells = <0>;
588 reg = <0xffc02500 0x100>;
589 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
597 #size-cells = <0>;
599 reg = <0xffc02600 0x100>;
600 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
609 #size-cells = <0>;
610 reg = <0xffda4000 0x100>;
611 interrupts = <0 101 4>;
623 #size-cells = <0>;
624 reg = <0xffda5000 0x100>;
625 interrupts = <0 102 4>;
638 reg = <0xffcfb100 0x80>;
643 reg = <0xfffff000 0x1000>;
644 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
654 #size-cells = <0>;
656 reg = <0xff808000 0x1000>;
657 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
658 fifo-depth = <0x400>;
667 #size-cells = <0>;
669 reg = <0xffb90000 0x72000>,
670 <0xffb80000 0x10000>;
672 interrupts = <0 99 4>;
681 reg = <0xffe00000 0x40000>;
689 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
690 <0 0 IRQ_TYPE_LEVEL_HIGH>;
704 reg = <0xffd06010 0x4>;
705 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
711 reg = <0xff8c3000 0x400>;
718 reg = <0xff8c0800 0x400>;
726 reg = <0xff8c0c00 0x400>;
734 reg = <0xff8c8000 0x400>;
742 reg = <0xff8c8800 0x400>;
752 #size-cells = <0>;
753 reg = <0xff809000 0x100>,
754 <0xffa00000 0x100000>;
755 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
758 cdns,trigger-address = <0x00000000>;
768 reg = <0xffd05000 0x100>;
769 altr,modrst-offset = <0x20>;
774 reg = <0xffffc000 0x100>;
779 reg = <0xffd06000 0x300>;
780 cpu1-start-addr = <0xffd06230>;
786 reg = <0xffffc600 0x100>;
787 interrupts = <1 13 0xf01>;
793 interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
794 reg = <0xffc02700 0x100>;
803 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
804 reg = <0xffc02800 0x100>;
813 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
814 reg = <0xffd00000 0x100>;
823 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
824 reg = <0xffd00100 0x100>;
833 reg = <0xffc02000 0x100>;
834 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
844 reg = <0xffc02100 0x100>;
845 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
854 #phy-cells = <0>;
861 reg = <0xffb00000 0xffff>;
862 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
874 reg = <0xffb40000 0xffff>;
875 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
887 reg = <0xffd00200 0x100>;
888 interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
896 reg = <0xffd00300 0x100>;
897 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;