Lines Matching +full:- +full:compatible
1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
27 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
36 next-level-cache = <&L2>;
41 compatible = "arm,cortex-a9-pmu";
42 interrupt-parent = <&intc>;
44 interrupt-affinity = <&cpu0>, <&cpu1>;
50 compatible = "arm,cortex-a9-gic";
51 #interrupt-cells = <3>;
52 interrupt-controller;
58 #address-cells = <1>;
59 #size-cells = <1>;
60 compatible = "simple-bus";
62 interrupt-parent = <&intc>;
66 compatible = "simple-bus";
67 #address-cells = <1>;
68 #size-cells = <1>;
72 compatible = "arm,pl330", "arm,primecell";
82 #dma-cells = <1>;
83 #dma-channels = <8>;
84 #dma-requests = <32>;
86 clock-names = "apb_pclk";
88 reset-names = "dma";
93 compatible = "fpga-region";
94 fpga-mgr = <&fpgamgr0>;
96 #address-cells = <0x1>;
97 #size-cells = <0x1>;
101 compatible = "bosch,d_can";
110 compatible = "bosch,d_can";
119 compatible = "altr,clk-mgr";
123 #address-cells = <1>;
124 #size-cells = <0>;
127 #clock-cells = <0>;
128 compatible = "fixed-clock";
132 #clock-cells = <0>;
133 compatible = "fixed-clock";
137 #clock-cells = <0>;
138 compatible = "fixed-clock";
142 #clock-cells = <0>;
143 compatible = "fixed-clock";
147 #address-cells = <1>;
148 #size-cells = <0>;
149 #clock-cells = <0>;
150 compatible = "altr,socfpga-pll-clock";
155 #clock-cells = <0>;
156 compatible = "altr,socfpga-perip-clk";
158 div-reg = <0xe0 0 9>;
163 #clock-cells = <0>;
164 compatible = "altr,socfpga-perip-clk";
166 div-reg = <0xe4 0 9>;
171 #clock-cells = <0>;
172 compatible = "altr,socfpga-perip-clk";
174 div-reg = <0xe8 0 9>;
179 #clock-cells = <0>;
180 compatible = "altr,socfpga-perip-clk";
186 #clock-cells = <0>;
187 compatible = "altr,socfpga-perip-clk";
193 #clock-cells = <0>;
194 compatible = "altr,socfpga-perip-clk";
201 #address-cells = <1>;
202 #size-cells = <0>;
203 #clock-cells = <0>;
204 compatible = "altr,socfpga-pll-clock";
209 #clock-cells = <0>;
210 compatible = "altr,socfpga-perip-clk";
216 #clock-cells = <0>;
217 compatible = "altr,socfpga-perip-clk";
223 #clock-cells = <0>;
224 compatible = "altr,socfpga-perip-clk";
230 #clock-cells = <0>;
231 compatible = "altr,socfpga-perip-clk";
237 #clock-cells = <0>;
238 compatible = "altr,socfpga-perip-clk";
244 #clock-cells = <0>;
245 compatible = "altr,socfpga-perip-clk";
252 #address-cells = <1>;
253 #size-cells = <0>;
254 #clock-cells = <0>;
255 compatible = "altr,socfpga-pll-clock";
260 #clock-cells = <0>;
261 compatible = "altr,socfpga-perip-clk";
267 #clock-cells = <0>;
268 compatible = "altr,socfpga-perip-clk";
274 #clock-cells = <0>;
275 compatible = "altr,socfpga-perip-clk";
281 #clock-cells = <0>;
282 compatible = "altr,socfpga-perip-clk";
289 #clock-cells = <0>;
290 compatible = "altr,socfpga-perip-clk";
292 fixed-divider = <4>;
296 #clock-cells = <0>;
297 compatible = "altr,socfpga-perip-clk";
299 fixed-divider = <2>;
303 #clock-cells = <0>;
304 compatible = "altr,socfpga-gate-clk";
306 clk-gate = <0x60 0>;
310 #clock-cells = <0>;
311 compatible = "altr,socfpga-perip-clk";
313 fixed-divider = <1>;
317 #clock-cells = <0>;
318 compatible = "altr,socfpga-gate-clk";
320 div-reg = <0x64 0 2>;
321 clk-gate = <0x60 1>;
325 #clock-cells = <0>;
326 compatible = "altr,socfpga-gate-clk";
328 div-reg = <0x64 2 2>;
332 #clock-cells = <0>;
333 compatible = "altr,socfpga-gate-clk";
335 div-reg = <0x64 4 3>;
336 clk-gate = <0x60 2>;
340 #clock-cells = <0>;
341 compatible = "altr,socfpga-gate-clk";
343 div-reg = <0x64 7 3>;
344 clk-gate = <0x60 3>;
348 #clock-cells = <0>;
349 compatible = "altr,socfpga-gate-clk";
351 div-reg = <0x68 0 2>;
352 clk-gate = <0x60 4>;
356 #clock-cells = <0>;
357 compatible = "altr,socfpga-gate-clk";
359 div-reg = <0x68 2 2>;
360 clk-gate = <0x60 5>;
364 #clock-cells = <0>;
365 compatible = "altr,socfpga-gate-clk";
367 div-reg = <0x6C 0 3>;
368 clk-gate = <0x60 6>;
372 #clock-cells = <0>;
373 compatible = "altr,socfpga-gate-clk";
375 clk-gate = <0x60 7>;
379 #clock-cells = <0>;
380 compatible = "altr,socfpga-gate-clk";
382 clk-gate = <0x60 8>;
386 #clock-cells = <0>;
387 compatible = "altr,socfpga-gate-clk";
389 clk-gate = <0x60 9>;
393 #clock-cells = <0>;
394 compatible = "altr,socfpga-gate-clk";
396 clk-gate = <0xa0 0>;
400 #clock-cells = <0>;
401 compatible = "altr,socfpga-gate-clk";
403 clk-gate = <0xa0 1>;
407 #clock-cells = <0>;
408 compatible = "altr,socfpga-gate-clk";
410 clk-gate = <0xa0 2>;
411 div-reg = <0xa4 0 3>;
415 #clock-cells = <0>;
416 compatible = "altr,socfpga-gate-clk";
418 clk-gate = <0xa0 3>;
419 div-reg = <0xa4 3 3>;
423 #clock-cells = <0>;
424 compatible = "altr,socfpga-gate-clk";
426 clk-gate = <0xa0 4>;
427 div-reg = <0xa4 6 3>;
431 #clock-cells = <0>;
432 compatible = "altr,socfpga-gate-clk";
434 clk-gate = <0xa0 5>;
435 div-reg = <0xa4 9 3>;
439 #clock-cells = <0>;
440 compatible = "altr,socfpga-gate-clk";
442 clk-gate = <0xa0 6>;
443 div-reg = <0xa8 0 24>;
447 #clock-cells = <0>;
448 compatible = "altr,socfpga-gate-clk";
450 clk-gate = <0xa0 7>;
454 #clock-cells = <0>;
455 compatible = "altr,socfpga-gate-clk";
457 clk-gate = <0xa0 8>;
458 clk-phase = <0 135>;
462 #clock-cells = <0>;
463 compatible = "altr,socfpga-gate-clk";
465 clk-gate = <0xa0 8>;
466 fixed-divider = <4>;
470 #clock-cells = <0>;
471 compatible = "altr,socfpga-gate-clk";
473 clk-gate = <0xa0 9>;
477 #clock-cells = <0>;
478 compatible = "altr,socfpga-gate-clk";
480 clk-gate = <0xa0 9>;
484 #clock-cells = <0>;
485 compatible = "altr,socfpga-gate-clk";
487 clk-gate = <0xa0 10>;
488 fixed-divider = <4>;
492 #clock-cells = <0>;
493 compatible = "altr,socfpga-gate-clk";
495 clk-gate = <0xa0 11>;
499 #clock-cells = <0>;
500 compatible = "altr,socfpga-gate-clk";
502 clk-gate = <0xd8 0>;
506 #clock-cells = <0>;
507 compatible = "altr,socfpga-gate-clk";
509 clk-gate = <0xd8 1>;
513 #clock-cells = <0>;
514 compatible = "altr,socfpga-gate-clk";
516 clk-gate = <0xd8 2>;
520 #clock-cells = <0>;
521 compatible = "altr,socfpga-gate-clk";
523 clk-gate = <0xd8 3>;
530 compatible = "altr,socfpga-lwhps2fpga-bridge";
538 compatible = "altr,socfpga-hps2fpga-bridge";
545 fpga_bridge2: fpga-bridge@ff600000 {
546 compatible = "altr,socfpga-fpga2hps-bridge";
553 fpga_bridge3: fpga-bridge@ffc25080 {
554 compatible = "altr,socfpga-fpga2sdram-bridge";
560 compatible = "altr,socfpga-fpga-mgr";
567 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
568 altr,sysmgr-syscon = <&sysmgr 0x60 0>;
571 interrupt-names = "macirq";
572 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
574 clock-names = "stmmaceth";
576 reset-names = "stmmaceth";
577 snps,multicast-filter-bins = <256>;
578 snps,perfect-filter-entries = <128>;
579 tx-fifo-depth = <4096>;
580 rx-fifo-depth = <4096>;
585 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
586 altr,sysmgr-syscon = <&sysmgr 0x60 2>;
589 interrupt-names = "macirq";
590 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
592 clock-names = "stmmaceth";
594 reset-names = "stmmaceth";
595 snps,multicast-filter-bins = <256>;
596 snps,perfect-filter-entries = <128>;
597 tx-fifo-depth = <4096>;
598 rx-fifo-depth = <4096>;
603 #address-cells = <1>;
604 #size-cells = <0>;
605 compatible = "snps,dw-apb-gpio";
611 porta: gpio-controller@0 {
612 compatible = "snps,dw-apb-gpio-port";
613 gpio-controller;
614 #gpio-cells = <2>;
615 snps,nr-gpios = <29>;
617 interrupt-controller;
618 #interrupt-cells = <2>;
624 #address-cells = <1>;
625 #size-cells = <0>;
626 compatible = "snps,dw-apb-gpio";
632 portb: gpio-controller@0 {
633 compatible = "snps,dw-apb-gpio-port";
634 gpio-controller;
635 #gpio-cells = <2>;
636 snps,nr-gpios = <29>;
638 interrupt-controller;
639 #interrupt-cells = <2>;
645 #address-cells = <1>;
646 #size-cells = <0>;
647 compatible = "snps,dw-apb-gpio";
653 portc: gpio-controller@0 {
654 compatible = "snps,dw-apb-gpio-port";
655 gpio-controller;
656 #gpio-cells = <2>;
657 snps,nr-gpios = <27>;
659 interrupt-controller;
660 #interrupt-cells = <2>;
666 #address-cells = <1>;
667 #size-cells = <0>;
668 compatible = "snps,designware-i2c";
677 #address-cells = <1>;
678 #size-cells = <0>;
679 compatible = "snps,designware-i2c";
688 #address-cells = <1>;
689 #size-cells = <0>;
690 compatible = "snps,designware-i2c";
699 #address-cells = <1>;
700 #size-cells = <0>;
701 compatible = "snps,designware-i2c";
710 compatible = "altr,socfpga-ecc-manager";
711 #address-cells = <1>;
712 #size-cells = <1>;
715 l2-ecc@ffd08140 {
716 compatible = "altr,socfpga-l2-ecc";
721 ocram-ecc@ffd08144 {
722 compatible = "altr,socfpga-ocram-ecc";
729 L2: cache-controller@fffef000 {
730 compatible = "arm,pl310-cache";
733 cache-unified;
734 cache-level = <2>;
735 arm,tag-latency = <1 1 1>;
736 arm,data-latency = <2 1 1>;
737 prefetch-data = <1>;
738 prefetch-instr = <1>;
739 arm,shared-override;
740 arm,double-linefill = <1>;
741 arm,double-linefill-incr = <0>;
742 arm,double-linefill-wrap = <1>;
743 arm,prefetch-drop = <0>;
744 arm,prefetch-offset = <7>;
748 compatible = "altr,l3regs", "syscon";
753 compatible = "altr,socfpga-dw-mshc";
756 fifo-depth = <0x400>;
757 #address-cells = <1>;
758 #size-cells = <0>;
760 clock-names = "biu", "ciu";
766 #address-cells = <0x1>;
767 #size-cells = <0x0>;
768 compatible = "altr,socfpga-denali-nand";
771 reg-names = "nand_data", "denali_reg";
774 clock-names = "nand", "nand_x", "ecc";
780 compatible = "mmio-sram";
785 compatible = "cdns,qspi-nor";
786 #address-cells = <1>;
787 #size-cells = <0>;
791 cdns,fifo-depth = <128>;
792 cdns,fifo-width = <4>;
793 cdns,trigger-address = <0x00000000>;
800 #reset-cells = <1>;
801 compatible = "altr,rst-mgr";
803 altr,modrst-offset = <0x10>;
806 scu: snoop-control-unit@fffec000 {
807 compatible = "arm,cortex-a9-scu";
812 compatible = "altr,sdr-ctl", "syscon";
818 compatible = "altr,sdram-edac";
819 altr,sdr-syscon = <&sdr>;
824 compatible = "snps,dw-apb-ssi";
825 #address-cells = <1>;
826 #size-cells = <0>;
829 num-cs = <4>;
832 reset-names = "spi";
837 compatible = "snps,dw-apb-ssi";
838 #address-cells = <1>;
839 #size-cells = <0>;
842 num-cs = <4>;
845 reset-names = "spi";
850 compatible = "altr,sys-mgr", "syscon";
856 compatible = "arm,cortex-a9-twd-timer";
863 compatible = "snps,dw-apb-timer";
867 clock-names = "timer";
869 reset-names = "timer";
873 compatible = "snps,dw-apb-timer";
877 clock-names = "timer";
879 reset-names = "timer";
883 compatible = "snps,dw-apb-timer";
887 clock-names = "timer";
889 reset-names = "timer";
893 compatible = "snps,dw-apb-timer";
897 clock-names = "timer";
899 reset-names = "timer";
903 compatible = "snps,dw-apb-uart";
906 reg-shift = <2>;
907 reg-io-width = <4>;
911 dma-names = "tx", "rx";
916 compatible = "snps,dw-apb-uart";
919 reg-shift = <2>;
920 reg-io-width = <4>;
924 dma-names = "tx", "rx";
929 #phy-cells = <0>;
930 compatible = "usb-nop-xceiv";
935 compatible = "snps,dwc2";
939 clock-names = "otg";
941 reset-names = "dwc2";
943 phy-names = "usb2-phy";
948 compatible = "snps,dwc2";
952 clock-names = "otg";
954 reset-names = "dwc2";
956 phy-names = "usb2-phy";
961 compatible = "snps,dw-wdt";
970 compatible = "snps,dw-wdt";