Lines Matching +full:0 +full:x800
36 #size-cells = <0>;
38 cpu@0 {
41 reg = <0>;
47 reg = <0x20000000 0x10000000>;
53 #clock-cells = <0>;
58 #clock-cells = <0>;
64 reg = <0x00300000 0x100000>;
67 ranges = <0 0x00300000 0x100000>;
78 #size-cells = <0>;
80 reg = <0x00500000 0x100000
81 0xf803c000 0x400>;
92 reg = <0x00600000 0x100000>;
101 reg = <0x00700000 0x100000>;
116 reg = <0x10000000 0x60000000>;
117 ranges = <0x0 0x0 0x10000000 0x10000000
118 0x1 0x0 0x20000000 0x10000000
119 0x2 0x0 0x30000000 0x10000000
120 0x3 0x0 0x40000000 0x10000000
121 0x4 0x0 0x50000000 0x10000000
122 0x5 0x0 0x60000000 0x10000000>;
138 reg = <0x80000000 0x300>;
139 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
149 reg = <0x90000000 0x300>;
150 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
166 reg = <0xf0000000 0x200>;
170 ranges = <0x0 0xf0000000 0x800>;
176 reg = <0xf0004000 0x200>;
180 ranges = <0x0 0xf0004000 0x800>;
186 reg = <0xf0008000 0x1000>;
187 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
195 reg = <0xf0010000 0x4000>;
198 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
201 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
211 reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
215 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
218 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
225 #size-cells = <0>;
231 reg = <0xf001c000 0x100>;
234 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
237 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
247 reg = <0xf0020000 0x200>;
251 ranges = <0x0 0xf0020000 0x800>;
257 reg = <0xf0024000 0x200>;
261 ranges = <0x0 0xf0024000 0x800>;
267 reg = <0xf0028000 0x100>;
275 reg = <0xf002c000 0x100>;
276 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
278 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
288 reg = <0xf0030000 0x100>;
289 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
296 reg = <0xf0034000 0x100>;
297 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
299 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
302 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
312 reg = <0xf0038000 0x100>;
313 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
315 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
318 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
328 reg = <0xf003c000 0x100>;
331 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
341 reg = <0xf8000000 0x300>;
350 reg = <0xf8004000 0x300>;
360 #size-cells = <0>;
361 reg = <0xf8008000 0x100>;
362 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
363 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>;
370 #size-cells = <0>;
371 reg = <0xf800c000 0x100>;
372 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
373 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k 0>;
379 reg = <0xf8010000 0x200>;
383 ranges = <0x0 0xf8010000 0x800>;
389 reg = <0xf8014000 0x200>;
393 ranges = <0x0 0xf8014000 0x800>;
399 reg = <0xf8018000 0x200>;
403 ranges = <0x0 0xf8018000 0x800>;
409 reg = <0xf801c000 0x200>;
413 ranges = <0x0 0xf801c000 0x800>;
419 reg = <0xf8020000 0x200>;
423 ranges = <0x0 0xf8020000 0x800>;
429 reg = <0xf8024000 0x200>;
433 ranges = <0x0 0xf8024000 0x800>;
439 reg = <0xf8028000 0x200>;
443 ranges = <0x0 0xf8028000 0x800>;
449 reg = <0xf802c000 0x1000>;
458 reg = <0xf8030000 0x1000>;
467 reg = <0xf8034000 0x300>;
476 reg = <0xf8038000 0x4000>;
477 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
487 #size-cells = <0>;
489 port@0 {
491 #size-cells = <0>;
492 reg = <0>;
504 reg = <0xf8040000 0x200>;
508 ranges = <0x0 0xf8040000 0x800>;
514 reg = <0xf8044000 0x200>;
518 ranges = <0x0 0xf8044000 0x800>;
524 reg = <0xf8048000 0x100>;
531 #size-cells = <0>;
537 reg = <0xf804c000 0x100>;
541 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>;
553 reg = <0xf8050000 0x100>;
558 reg = <0xffffde00 0x200>;
563 reg = <0xffffe000 0x300>,
564 <0xffffe600 0x100>;
569 reg = <0xffffe800 0x200>;
576 reg = <0xffffea00 0x100>;
583 reg = <0xfffff100 0x100>;
589 reg = <0xfffff200 0x200>;
592 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
595 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
607 ranges = <0xfffff400 0xfffff400 0x800>;
611 reg = <0xfffff400 0x200>;
622 reg = <0xfffff600 0x200>;
634 reg = <0xfffff800 0x200>;
645 reg = <0xfffffa00 0x200>;
658 reg = <0xfffffc00 0x200>;
661 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
667 reg = <0xfffffe00 0x10>;
668 clocks = <&clk32k 0>;
673 reg = <0xfffffe10 0x10>;
674 clocks = <&clk32k 0>;
676 #size-cells = <0>;
684 reg = <0xfffffe20 0x20>;
686 clocks = <&clk32k 0>;
691 reg = <0xfffffe40 0x10>;
698 reg = <0xfffffe50 0x4>;
705 reg = <0xfffffe60 0x10>;
710 reg = <0xfffffea8 0x100>;
712 clocks = <&clk32k 0>;
717 reg = <0xffffff80 0x24>;
719 clocks = <&clk32k 0>;