Lines Matching full:cru
49 clocks = <&cru ACLK_DMA1>;
61 clocks = <&cru ACLK_DMA1>;
74 clocks = <&cru ACLK_DMA2>;
89 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
91 assigned-clocks = <&cru ACLK_GPU>;
93 resets = <&cru SRST_GPU>;
113 clocks = <&cru CORE_PERI>;
120 clocks = <&cru CORE_PERI>;
138 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
149 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
197 clocks = <&cru HCLK_OTG0>;
212 clocks = <&cru HCLK_OTG1>;
229 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
241 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
246 resets = <&cru SRST_SDMMC>;
255 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
260 resets = <&cru SRST_SDIO>;
269 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
274 resets = <&cru SRST_EMMC>;
308 clocks = <&cru PCLK_I2C0>;
322 clocks = <&cru PCLK_I2C1>;
332 clocks = <&cru PCLK_PWM01>;
340 clocks = <&cru PCLK_PWM01>;
347 clocks = <&cru PCLK_WDT>;
356 clocks = <&cru PCLK_PWM23>;
364 clocks = <&cru PCLK_PWM23>;
377 clocks = <&cru PCLK_I2C2>;
392 clocks = <&cru PCLK_I2C3>;
407 clocks = <&cru PCLK_I2C4>;
420 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
431 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
440 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
442 resets = <&cru SRST_SARADC>;
449 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
462 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;