Lines Matching +full:rk3066 +full:- +full:smp
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power/rk3288-power.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
18 interrupt-parent = <&gic>;
42 arm-pmu {
43 compatible = "arm,cortex-a12-pmu";
48 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
52 #address-cells = <1>;
53 #size-cells = <0>;
54 enable-method = "rockchip,rk3066-smp";
59 compatible = "arm,cortex-a12";
62 operating-points-v2 = <&cpu_opp_table>;
63 #cooling-cells = <2>; /* min followed by max */
64 clock-latency = <40000>;
66 dynamic-power-coefficient = <370>;
70 compatible = "arm,cortex-a12";
73 operating-points-v2 = <&cpu_opp_table>;
74 #cooling-cells = <2>; /* min followed by max */
75 clock-latency = <40000>;
77 dynamic-power-coefficient = <370>;
81 compatible = "arm,cortex-a12";
84 operating-points-v2 = <&cpu_opp_table>;
85 #cooling-cells = <2>; /* min followed by max */
86 clock-latency = <40000>;
88 dynamic-power-coefficient = <370>;
92 compatible = "arm,cortex-a12";
95 operating-points-v2 = <&cpu_opp_table>;
96 #cooling-cells = <2>; /* min followed by max */
97 clock-latency = <40000>;
99 dynamic-power-coefficient = <370>;
103 cpu_opp_table: cpu-opp-table {
104 compatible = "operating-points-v2";
105 opp-shared;
107 opp-126000000 {
108 opp-hz = /bits/ 64 <126000000>;
109 opp-microvolt = <900000>;
111 opp-216000000 {
112 opp-hz = /bits/ 64 <216000000>;
113 opp-microvolt = <900000>;
115 opp-312000000 {
116 opp-hz = /bits/ 64 <312000000>;
117 opp-microvolt = <900000>;
119 opp-408000000 {
120 opp-hz = /bits/ 64 <408000000>;
121 opp-microvolt = <900000>;
123 opp-600000000 {
124 opp-hz = /bits/ 64 <600000000>;
125 opp-microvolt = <900000>;
127 opp-696000000 {
128 opp-hz = /bits/ 64 <696000000>;
129 opp-microvolt = <950000>;
131 opp-816000000 {
132 opp-hz = /bits/ 64 <816000000>;
133 opp-microvolt = <1000000>;
135 opp-1008000000 {
136 opp-hz = /bits/ 64 <1008000000>;
137 opp-microvolt = <1050000>;
139 opp-1200000000 {
140 opp-hz = /bits/ 64 <1200000000>;
141 opp-microvolt = <1100000>;
143 opp-1416000000 {
144 opp-hz = /bits/ 64 <1416000000>;
145 opp-microvolt = <1200000>;
147 opp-1512000000 {
148 opp-hz = /bits/ 64 <1512000000>;
149 opp-microvolt = <1300000>;
151 opp-1608000000 {
152 opp-hz = /bits/ 64 <1608000000>;
153 opp-microvolt = <1350000>;
158 compatible = "simple-bus";
159 #address-cells = <2>;
160 #size-cells = <2>;
163 dmac_peri: dma-controller@ff250000 {
168 #dma-cells = <1>;
169 arm,pl330-broken-no-flushp;
170 arm,pl330-periph-burst;
172 clock-names = "apb_pclk";
175 dmac_bus_ns: dma-controller@ff600000 {
180 #dma-cells = <1>;
181 arm,pl330-broken-no-flushp;
182 arm,pl330-periph-burst;
184 clock-names = "apb_pclk";
188 dmac_bus_s: dma-controller@ffb20000 {
193 #dma-cells = <1>;
194 arm,pl330-broken-no-flushp;
195 arm,pl330-periph-burst;
197 clock-names = "apb_pclk";
201 reserved-memory {
202 #address-cells = <2>;
203 #size-cells = <2>;
216 dma-unusable@fe000000 {
222 compatible = "fixed-clock";
223 clock-frequency = <24000000>;
224 clock-output-names = "xin24m";
225 #clock-cells = <0>;
229 compatible = "arm,armv7-timer";
230 arm,cpu-registers-not-fw-configured;
235 clock-frequency = <24000000>;
236 arm,no-tick-in-suspend;
240 compatible = "rockchip,rk3288-timer";
244 clock-names = "timer", "pclk";
247 display-subsystem {
248 compatible = "rockchip,display-subsystem";
253 compatible = "rockchip,rk3288-dw-mshc";
254 max-frequency = <150000000>;
257 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
258 fifo-depth = <0x100>;
262 reset-names = "reset";
267 compatible = "rockchip,rk3288-dw-mshc";
268 max-frequency = <150000000>;
271 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
272 fifo-depth = <0x100>;
276 reset-names = "reset";
281 compatible = "rockchip,rk3288-dw-mshc";
282 max-frequency = <150000000>;
285 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
286 fifo-depth = <0x100>;
290 reset-names = "reset";
295 compatible = "rockchip,rk3288-dw-mshc";
296 max-frequency = <150000000>;
299 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
300 fifo-depth = <0x100>;
304 reset-names = "reset";
312 #io-channel-cells = <1>;
314 clock-names = "saradc", "apb_pclk";
316 reset-names = "saradc-apb";
321 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
323 clock-names = "spiclk", "apb_pclk";
325 dma-names = "tx", "rx";
327 pinctrl-names = "default";
328 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
330 #address-cells = <1>;
331 #size-cells = <0>;
336 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
338 clock-names = "spiclk", "apb_pclk";
340 dma-names = "tx", "rx";
342 pinctrl-names = "default";
343 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
345 #address-cells = <1>;
346 #size-cells = <0>;
351 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
353 clock-names = "spiclk", "apb_pclk";
355 dma-names = "tx", "rx";
357 pinctrl-names = "default";
358 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
360 #address-cells = <1>;
361 #size-cells = <0>;
366 compatible = "rockchip,rk3288-i2c";
369 #address-cells = <1>;
370 #size-cells = <0>;
371 clock-names = "i2c";
373 pinctrl-names = "default";
374 pinctrl-0 = <&i2c1_xfer>;
379 compatible = "rockchip,rk3288-i2c";
382 #address-cells = <1>;
383 #size-cells = <0>;
384 clock-names = "i2c";
386 pinctrl-names = "default";
387 pinctrl-0 = <&i2c3_xfer>;
392 compatible = "rockchip,rk3288-i2c";
395 #address-cells = <1>;
396 #size-cells = <0>;
397 clock-names = "i2c";
399 pinctrl-names = "default";
400 pinctrl-0 = <&i2c4_xfer>;
405 compatible = "rockchip,rk3288-i2c";
408 #address-cells = <1>;
409 #size-cells = <0>;
410 clock-names = "i2c";
412 pinctrl-names = "default";
413 pinctrl-0 = <&i2c5_xfer>;
418 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
421 reg-shift = <2>;
422 reg-io-width = <4>;
424 clock-names = "baudclk", "apb_pclk";
426 dma-names = "tx", "rx";
427 pinctrl-names = "default";
428 pinctrl-0 = <&uart0_xfer>;
433 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
436 reg-shift = <2>;
437 reg-io-width = <4>;
439 clock-names = "baudclk", "apb_pclk";
441 dma-names = "tx", "rx";
442 pinctrl-names = "default";
443 pinctrl-0 = <&uart1_xfer>;
448 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
451 reg-shift = <2>;
452 reg-io-width = <4>;
454 clock-names = "baudclk", "apb_pclk";
455 pinctrl-names = "default";
456 pinctrl-0 = <&uart2_xfer>;
461 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
464 reg-shift = <2>;
465 reg-io-width = <4>;
467 clock-names = "baudclk", "apb_pclk";
469 dma-names = "tx", "rx";
470 pinctrl-names = "default";
471 pinctrl-0 = <&uart3_xfer>;
476 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
479 reg-shift = <2>;
480 reg-io-width = <4>;
482 clock-names = "baudclk", "apb_pclk";
484 dma-names = "tx", "rx";
485 pinctrl-names = "default";
486 pinctrl-0 = <&uart4_xfer>;
490 thermal-zones {
492 polling-delay-passive = <1000>; /* milliseconds */
493 polling-delay = <5000>; /* milliseconds */
495 thermal-sensors = <&tsadc 0>;
499 polling-delay-passive = <100>; /* milliseconds */
500 polling-delay = <5000>; /* milliseconds */
502 thermal-sensors = <&tsadc 1>;
522 cooling-maps {
525 cooling-device =
533 cooling-device =
543 polling-delay-passive = <100>; /* milliseconds */
544 polling-delay = <5000>; /* milliseconds */
546 thermal-sensors = <&tsadc 2>;
561 cooling-maps {
564 cooling-device =
572 compatible = "rockchip,rk3288-tsadc";
576 clock-names = "tsadc", "apb_pclk";
578 reset-names = "tsadc-apb";
579 pinctrl-names = "init", "default", "sleep";
580 pinctrl-0 = <&otp_pin>;
581 pinctrl-1 = <&otp_out>;
582 pinctrl-2 = <&otp_pin>;
583 #thermal-sensor-cells = <1>;
585 rockchip,hw-tshut-temp = <95000>;
590 compatible = "rockchip,rk3288-gmac";
594 interrupt-names = "macirq", "eth_wake_irq";
600 clock-names = "stmmaceth",
605 reset-names = "stmmaceth";
610 compatible = "generic-ehci";
615 phy-names = "usb";
621 compatible = "generic-ohci";
626 phy-names = "usb";
631 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
636 clock-names = "otg";
639 phy-names = "usb2-phy";
640 snps,reset-phy-on-wake;
645 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
650 clock-names = "otg";
652 g-np-tx-fifo-size = <16>;
653 g-rx-fifo-size = <275>;
654 g-tx-fifo-size = <256 128 128 64 64 32>;
656 phy-names = "usb2-phy";
661 compatible = "generic-ehci";
669 compatible = "rockchip,rk3288-i2c";
672 #address-cells = <1>;
673 #size-cells = <0>;
674 clock-names = "i2c";
676 pinctrl-names = "default";
677 pinctrl-0 = <&i2c0_xfer>;
682 compatible = "rockchip,rk3288-i2c";
685 #address-cells = <1>;
686 #size-cells = <0>;
687 clock-names = "i2c";
689 pinctrl-names = "default";
690 pinctrl-0 = <&i2c2_xfer>;
695 compatible = "rockchip,rk3288-pwm";
697 #pwm-cells = <3>;
698 pinctrl-names = "default";
699 pinctrl-0 = <&pwm0_pin>;
701 clock-names = "pwm";
706 compatible = "rockchip,rk3288-pwm";
708 #pwm-cells = <3>;
709 pinctrl-names = "default";
710 pinctrl-0 = <&pwm1_pin>;
712 clock-names = "pwm";
717 compatible = "rockchip,rk3288-pwm";
719 #pwm-cells = <3>;
720 pinctrl-names = "default";
721 pinctrl-0 = <&pwm2_pin>;
723 clock-names = "pwm";
728 compatible = "rockchip,rk3288-pwm";
730 #pwm-cells = <3>;
731 pinctrl-names = "default";
732 pinctrl-0 = <&pwm3_pin>;
734 clock-names = "pwm";
739 compatible = "mmio-sram";
741 #address-cells = <1>;
742 #size-cells = <1>;
744 smp-sram@0 {
745 compatible = "rockchip,rk3066-smp-sram";
751 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
755 pmu: power-management@ff730000 {
756 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
759 power: power-controller {
760 compatible = "rockchip,rk3288-power-controller";
761 #power-domain-cells = <1>;
762 #address-cells = <1>;
763 #size-cells = <0>;
765 assigned-clocks = <&cru SCLK_EDP_24M>;
766 assigned-clock-parents = <&xin24m>;
866 reboot-mode {
867 compatible = "syscon-reboot-mode";
869 mode-normal = <BOOT_NORMAL>;
870 mode-recovery = <BOOT_RECOVERY>;
871 mode-bootloader = <BOOT_FASTBOOT>;
872 mode-loader = <BOOT_BL_DOWNLOAD>;
877 compatible = "rockchip,rk3288-sgrf", "syscon";
881 cru: clock-controller@ff760000 {
882 compatible = "rockchip,rk3288-cru";
885 #clock-cells = <1>;
886 #reset-cells = <1>;
887 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
892 assigned-clock-rates = <594000000>, <400000000>,
900 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
903 edp_phy: edp-phy {
904 compatible = "rockchip,rk3288-dp-phy";
906 clock-names = "24m";
907 #phy-cells = <0>;
911 io_domains: io-domains {
912 compatible = "rockchip,rk3288-io-voltage-domain";
917 compatible = "rockchip,rk3288-usb-phy";
918 #address-cells = <1>;
919 #size-cells = <0>;
922 usbphy0: usb-phy@320 {
923 #phy-cells = <0>;
926 clock-names = "phyclk";
927 #clock-cells = <0>;
929 reset-names = "phy-reset";
932 usbphy1: usb-phy@334 {
933 #phy-cells = <0>;
936 clock-names = "phyclk";
937 #clock-cells = <0>;
939 reset-names = "phy-reset";
942 usbphy2: usb-phy@348 {
943 #phy-cells = <0>;
946 clock-names = "phyclk";
947 #clock-cells = <0>;
949 reset-names = "phy-reset";
955 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
963 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
965 #sound-dai-cells = <0>;
967 clock-names = "mclk", "hclk";
969 dma-names = "tx";
971 pinctrl-names = "default";
972 pinctrl-0 = <&spdif_tx>;
978 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
980 #sound-dai-cells = <0>;
983 clock-names = "i2s_clk", "i2s_hclk";
985 dma-names = "tx", "rx";
986 pinctrl-names = "default";
987 pinctrl-0 = <&i2s0_bus>;
988 rockchip,playback-channels = <8>;
989 rockchip,capture-channels = <2>;
993 crypto: cypto-controller@ff8a0000 {
994 compatible = "rockchip,rk3288-crypto";
999 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
1001 reset-names = "crypto-rst";
1009 interrupt-names = "iep_mmu";
1011 clock-names = "aclk", "iface";
1012 #iommu-cells = <0>;
1020 interrupt-names = "isp_mmu";
1022 clock-names = "aclk", "iface";
1023 #iommu-cells = <0>;
1024 rockchip,disable-mmu-reset;
1029 compatible = "rockchip,rk3288-rga";
1033 clock-names = "aclk", "hclk", "sclk";
1034 power-domains = <&power RK3288_PD_VIO>;
1036 reset-names = "core", "axi", "ahb";
1040 compatible = "rockchip,rk3288-vop";
1044 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1045 power-domains = <&power RK3288_PD_VIO>;
1047 reset-names = "axi", "ahb", "dclk";
1052 #address-cells = <1>;
1053 #size-cells = <0>;
1057 remote-endpoint = <&hdmi_in_vopb>;
1062 remote-endpoint = <&edp_in_vopb>;
1067 remote-endpoint = <&mipi_in_vopb>;
1072 remote-endpoint = <&lvds_in_vopb>;
1081 interrupt-names = "vopb_mmu";
1083 clock-names = "aclk", "iface";
1084 power-domains = <&power RK3288_PD_VIO>;
1085 #iommu-cells = <0>;
1090 compatible = "rockchip,rk3288-vop";
1094 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1095 power-domains = <&power RK3288_PD_VIO>;
1097 reset-names = "axi", "ahb", "dclk";
1102 #address-cells = <1>;
1103 #size-cells = <0>;
1107 remote-endpoint = <&hdmi_in_vopl>;
1112 remote-endpoint = <&edp_in_vopl>;
1117 remote-endpoint = <&mipi_in_vopl>;
1122 remote-endpoint = <&lvds_in_vopl>;
1131 interrupt-names = "vopl_mmu";
1133 clock-names = "aclk", "iface";
1134 power-domains = <&power RK3288_PD_VIO>;
1135 #iommu-cells = <0>;
1140 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1144 clock-names = "ref", "pclk";
1145 power-domains = <&power RK3288_PD_VIO>;
1151 #address-cells = <1>;
1152 #size-cells = <0>;
1155 remote-endpoint = <&vopb_out_mipi>;
1159 remote-endpoint = <&vopl_out_mipi>;
1166 compatible = "rockchip,rk3288-lvds";
1169 clock-names = "pclk_lvds";
1170 pinctrl-names = "lcdc";
1171 pinctrl-0 = <&lcdc_ctl>;
1172 power-domains = <&power RK3288_PD_VIO>;
1177 #address-cells = <1>;
1178 #size-cells = <0>;
1183 #address-cells = <1>;
1184 #size-cells = <0>;
1188 remote-endpoint = <&vopb_out_lvds>;
1192 remote-endpoint = <&vopl_out_lvds>;
1199 compatible = "rockchip,rk3288-dp";
1203 clock-names = "dp", "pclk";
1205 phy-names = "dp";
1207 reset-names = "dp";
1212 #address-cells = <1>;
1213 #size-cells = <0>;
1216 #address-cells = <1>;
1217 #size-cells = <0>;
1220 remote-endpoint = <&vopb_out_edp>;
1224 remote-endpoint = <&vopl_out_edp>;
1231 compatible = "rockchip,rk3288-dw-hdmi";
1233 reg-io-width = <4>;
1234 #sound-dai-cells = <0>;
1238 clock-names = "iahb", "isfr", "cec";
1239 power-domains = <&power RK3288_PD_VIO>;
1244 #address-cells = <1>;
1245 #size-cells = <0>;
1248 remote-endpoint = <&vopb_out_hdmi>;
1252 remote-endpoint = <&vopl_out_hdmi>;
1258 vpu: video-codec@ff9a0000 {
1259 compatible = "rockchip,rk3288-vpu";
1263 interrupt-names = "vepu", "vdpu";
1265 clock-names = "aclk", "hclk";
1267 power-domains = <&power RK3288_PD_VIDEO>;
1274 interrupt-names = "vpu_mmu";
1276 clock-names = "aclk", "iface";
1277 #iommu-cells = <0>;
1278 power-domains = <&power RK3288_PD_VIDEO>;
1285 interrupt-names = "hevc_mmu";
1287 clock-names = "aclk", "iface";
1288 #iommu-cells = <0>;
1293 compatible = "rockchip,rk3288-mali", "arm,mali-t760";
1298 interrupt-names = "job", "mmu", "gpu";
1300 operating-points-v2 = <&gpu_opp_table>;
1301 #cooling-cells = <2>; /* min followed by max */
1302 power-domains = <&power RK3288_PD_GPU>;
1306 gpu_opp_table: gpu-opp-table {
1307 compatible = "operating-points-v2";
1309 opp-100000000 {
1310 opp-hz = /bits/ 64 <100000000>;
1311 opp-microvolt = <950000>;
1313 opp-200000000 {
1314 opp-hz = /bits/ 64 <200000000>;
1315 opp-microvolt = <950000>;
1317 opp-300000000 {
1318 opp-hz = /bits/ 64 <300000000>;
1319 opp-microvolt = <1000000>;
1321 opp-400000000 {
1322 opp-hz = /bits/ 64 <400000000>;
1323 opp-microvolt = <1100000>;
1325 opp-600000000 {
1326 opp-hz = /bits/ 64 <600000000>;
1327 opp-microvolt = <1250000>;
1402 compatible = "rockchip,rk3288-efuse";
1404 #address-cells = <1>;
1405 #size-cells = <1>;
1407 clock-names = "pclk_efuse";
1409 cpu_id: cpu-id@7 {
1417 gic: interrupt-controller@ffc01000 {
1418 compatible = "arm,gic-400";
1419 interrupt-controller;
1420 #interrupt-cells = <3>;
1421 #address-cells = <0>;
1431 compatible = "rockchip,rk3288-pinctrl";
1434 #address-cells = <2>;
1435 #size-cells = <2>;
1439 compatible = "rockchip,gpio-bank";
1444 gpio-controller;
1445 #gpio-cells = <2>;
1447 interrupt-controller;
1448 #interrupt-cells = <2>;
1452 compatible = "rockchip,gpio-bank";
1457 gpio-controller;
1458 #gpio-cells = <2>;
1460 interrupt-controller;
1461 #interrupt-cells = <2>;
1465 compatible = "rockchip,gpio-bank";
1470 gpio-controller;
1471 #gpio-cells = <2>;
1473 interrupt-controller;
1474 #interrupt-cells = <2>;
1478 compatible = "rockchip,gpio-bank";
1483 gpio-controller;
1484 #gpio-cells = <2>;
1486 interrupt-controller;
1487 #interrupt-cells = <2>;
1491 compatible = "rockchip,gpio-bank";
1496 gpio-controller;
1497 #gpio-cells = <2>;
1499 interrupt-controller;
1500 #interrupt-cells = <2>;
1504 compatible = "rockchip,gpio-bank";
1509 gpio-controller;
1510 #gpio-cells = <2>;
1512 interrupt-controller;
1513 #interrupt-cells = <2>;
1517 compatible = "rockchip,gpio-bank";
1522 gpio-controller;
1523 #gpio-cells = <2>;
1525 interrupt-controller;
1526 #interrupt-cells = <2>;
1530 compatible = "rockchip,gpio-bank";
1535 gpio-controller;
1536 #gpio-cells = <2>;
1538 interrupt-controller;
1539 #interrupt-cells = <2>;
1543 compatible = "rockchip,gpio-bank";
1548 gpio-controller;
1549 #gpio-cells = <2>;
1551 interrupt-controller;
1552 #interrupt-cells = <2>;
1556 hdmi_cec_c0: hdmi-cec-c0 {
1560 hdmi_cec_c7: hdmi-cec-c7 {
1564 hdmi_ddc: hdmi-ddc {
1569 hdmi_ddc_unwedge: hdmi-ddc-unwedge {
1575 pcfg_output_low: pcfg-output-low {
1576 output-low;
1579 pcfg_pull_up: pcfg-pull-up {
1580 bias-pull-up;
1583 pcfg_pull_down: pcfg-pull-down {
1584 bias-pull-down;
1587 pcfg_pull_none: pcfg-pull-none {
1588 bias-disable;
1591 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1592 bias-disable;
1593 drive-strength = <12>;
1597 global_pwroff: global-pwroff {
1601 ddrio_pwroff: ddrio-pwroff {
1605 ddr0_retention: ddr0-retention {
1609 ddr1_retention: ddr1-retention {
1615 edp_hpd: edp-hpd {
1621 i2c0_xfer: i2c0-xfer {
1628 i2c1_xfer: i2c1-xfer {
1635 i2c2_xfer: i2c2-xfer {
1642 i2c3_xfer: i2c3-xfer {
1649 i2c4_xfer: i2c4-xfer {
1656 i2c5_xfer: i2c5-xfer {
1663 i2s0_bus: i2s0-bus {
1674 lcdc_ctl: lcdc-ctl {
1683 sdmmc_clk: sdmmc-clk {
1687 sdmmc_cmd: sdmmc-cmd {
1691 sdmmc_cd: sdmmc-cd {
1695 sdmmc_bus1: sdmmc-bus1 {
1699 sdmmc_bus4: sdmmc-bus4 {
1708 sdio0_bus1: sdio0-bus1 {
1712 sdio0_bus4: sdio0-bus4 {
1719 sdio0_cmd: sdio0-cmd {
1723 sdio0_clk: sdio0-clk {
1727 sdio0_cd: sdio0-cd {
1731 sdio0_wp: sdio0-wp {
1735 sdio0_pwr: sdio0-pwr {
1739 sdio0_bkpwr: sdio0-bkpwr {
1743 sdio0_int: sdio0-int {
1749 sdio1_bus1: sdio1-bus1 {
1753 sdio1_bus4: sdio1-bus4 {
1760 sdio1_cd: sdio1-cd {
1764 sdio1_wp: sdio1-wp {
1768 sdio1_bkpwr: sdio1-bkpwr {
1772 sdio1_int: sdio1-int {
1776 sdio1_cmd: sdio1-cmd {
1780 sdio1_clk: sdio1-clk {
1784 sdio1_pwr: sdio1-pwr {
1790 emmc_clk: emmc-clk {
1794 emmc_cmd: emmc-cmd {
1798 emmc_pwr: emmc-pwr {
1802 emmc_bus1: emmc-bus1 {
1806 emmc_bus4: emmc-bus4 {
1813 emmc_bus8: emmc-bus8 {
1826 spi0_clk: spi0-clk {
1829 spi0_cs0: spi0-cs0 {
1832 spi0_tx: spi0-tx {
1835 spi0_rx: spi0-rx {
1838 spi0_cs1: spi0-cs1 {
1843 spi1_clk: spi1-clk {
1846 spi1_cs0: spi1-cs0 {
1849 spi1_rx: spi1-rx {
1852 spi1_tx: spi1-tx {
1858 spi2_cs1: spi2-cs1 {
1861 spi2_clk: spi2-clk {
1864 spi2_cs0: spi2-cs0 {
1867 spi2_rx: spi2-rx {
1870 spi2_tx: spi2-tx {
1876 uart0_xfer: uart0-xfer {
1881 uart0_cts: uart0-cts {
1885 uart0_rts: uart0-rts {
1891 uart1_xfer: uart1-xfer {
1896 uart1_cts: uart1-cts {
1900 uart1_rts: uart1-rts {
1906 uart2_xfer: uart2-xfer {
1914 uart3_xfer: uart3-xfer {
1919 uart3_cts: uart3-cts {
1923 uart3_rts: uart3-rts {
1929 uart4_xfer: uart4-xfer {
1934 uart4_cts: uart4-cts {
1938 uart4_rts: uart4-rts {
1944 otp_pin: otp-pin {
1948 otp_out: otp-out {
1954 pwm0_pin: pwm0-pin {
1960 pwm1_pin: pwm1-pin {
1966 pwm2_pin: pwm2-pin {
1972 pwm3_pin: pwm3-pin {
1978 rgmii_pins: rgmii-pins {
1996 rmii_pins: rmii-pins {
2011 spdif_tx: spdif-tx {