Lines Matching full:cru
7 #include <dt-bindings/clock/rk3288-cru.h>
61 resets = <&cru SRST_CORE0>;
65 clocks = <&cru ARMCLK>;
72 resets = <&cru SRST_CORE1>;
76 clocks = <&cru ARMCLK>;
83 resets = <&cru SRST_CORE2>;
87 clocks = <&cru ARMCLK>;
94 resets = <&cru SRST_CORE3>;
98 clocks = <&cru ARMCLK>;
171 clocks = <&cru ACLK_DMAC2>;
183 clocks = <&cru ACLK_DMAC1>;
196 clocks = <&cru ACLK_DMAC1>;
243 clocks = <&xin24m>, <&cru PCLK_TIMER>;
255 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
256 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
261 resets = <&cru SRST_MMC0>;
269 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
270 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
275 resets = <&cru SRST_SDIO0>;
283 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
284 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
289 resets = <&cru SRST_SDIO1>;
297 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
298 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
303 resets = <&cru SRST_EMMC>;
313 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
315 resets = <&cru SRST_SARADC>;
322 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
337 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
352 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
372 clocks = <&cru PCLK_I2C1>;
385 clocks = <&cru PCLK_I2C3>;
398 clocks = <&cru PCLK_I2C4>;
411 clocks = <&cru PCLK_I2C5>;
423 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
438 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
453 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
466 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
481 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
575 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
577 resets = <&cru SRST_TSADC>;
596 clocks = <&cru SCLK_MAC>,
597 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
598 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
599 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
604 resets = <&cru SRST_MAC>;
613 clocks = <&cru HCLK_USBHOST0>;
624 clocks = <&cru HCLK_USBHOST0>;
635 clocks = <&cru HCLK_USBHOST1>;
649 clocks = <&cru HCLK_OTG0>;
664 clocks = <&cru HCLK_HSIC>;
675 clocks = <&cru PCLK_I2C0>;
688 clocks = <&cru PCLK_I2C2>;
700 clocks = <&cru PCLK_RKPWM>;
711 clocks = <&cru PCLK_RKPWM>;
722 clocks = <&cru PCLK_RKPWM>;
733 clocks = <&cru PCLK_RKPWM>;
765 assigned-clocks = <&cru SCLK_EDP_24M>;
793 clocks = <&cru ACLK_IEP>,
794 <&cru ACLK_ISP>,
795 <&cru ACLK_RGA>,
796 <&cru ACLK_VIP>,
797 <&cru ACLK_VOP0>,
798 <&cru ACLK_VOP1>,
799 <&cru DCLK_VOP0>,
800 <&cru DCLK_VOP1>,
801 <&cru HCLK_IEP>,
802 <&cru HCLK_ISP>,
803 <&cru HCLK_RGA>,
804 <&cru HCLK_VIP>,
805 <&cru HCLK_VOP0>,
806 <&cru HCLK_VOP1>,
807 <&cru PCLK_EDP_CTRL>,
808 <&cru PCLK_HDMI_CTRL>,
809 <&cru PCLK_LVDS_PHY>,
810 <&cru PCLK_MIPI_CSI>,
811 <&cru PCLK_MIPI_DSI0>,
812 <&cru PCLK_MIPI_DSI1>,
813 <&cru SCLK_EDP_24M>,
814 <&cru SCLK_EDP>,
815 <&cru SCLK_ISP_JPE>,
816 <&cru SCLK_ISP>,
817 <&cru SCLK_RGA>;
835 clocks = <&cru ACLK_HEVC>,
836 <&cru SCLK_HEVC_CABAC>,
837 <&cru SCLK_HEVC_CORE>;
849 clocks = <&cru ACLK_VCODEC>,
850 <&cru HCLK_VCODEC>;
860 clocks = <&cru ACLK_GPU>;
881 cru: clock-controller@ff760000 { label
882 compatible = "rockchip,rk3288-cru";
887 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
888 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
889 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
890 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
891 <&cru PCLK_PERI>;
905 clocks = <&cru SCLK_EDP_24M>;
925 clocks = <&cru SCLK_OTGPHY0>;
928 resets = <&cru SRST_USBOTG_PHY>;
935 clocks = <&cru SCLK_OTGPHY1>;
938 resets = <&cru SRST_USBHOST0_PHY>;
945 clocks = <&cru SCLK_OTGPHY2>;
948 resets = <&cru SRST_USBHOST1_PHY>;
957 clocks = <&cru PCLK_WDT>;
966 clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>;
982 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
997 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
998 <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
1000 resets = <&cru SRST_CRYPTO>;
1010 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1021 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1032 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1035 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1043 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1046 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1082 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1093 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1096 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1132 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1143 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1168 clocks = <&cru PCLK_LVDS_PHY>;
1202 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1206 resets = <&cru SRST_EDP>;
1237 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
1264 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1275 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1286 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
1299 clocks = <&cru ACLK_GPU>;
1406 clocks = <&cru PCLK_EFUSE256>;
1442 clocks = <&cru PCLK_GPIO0>;
1455 clocks = <&cru PCLK_GPIO1>;
1468 clocks = <&cru PCLK_GPIO2>;
1481 clocks = <&cru PCLK_GPIO3>;
1494 clocks = <&cru PCLK_GPIO4>;
1507 clocks = <&cru PCLK_GPIO5>;
1520 clocks = <&cru PCLK_GPIO6>;
1533 clocks = <&cru PCLK_GPIO7>;
1546 clocks = <&cru PCLK_GPIO8>;