Lines Matching +full:rk3288 +full:- +full:efuse
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3228-cru.h>
8 #include <dt-bindings/thermal/thermal.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&gic>;
24 #address-cells = <1>;
25 #size-cells = <0>;
29 compatible = "arm,cortex-a7";
32 operating-points-v2 = <&cpu0_opp_table>;
33 #cooling-cells = <2>; /* min followed by max */
34 clock-latency = <40000>;
36 enable-method = "psci";
41 compatible = "arm,cortex-a7";
44 operating-points-v2 = <&cpu0_opp_table>;
45 #cooling-cells = <2>; /* min followed by max */
46 enable-method = "psci";
51 compatible = "arm,cortex-a7";
54 operating-points-v2 = <&cpu0_opp_table>;
55 #cooling-cells = <2>; /* min followed by max */
56 enable-method = "psci";
61 compatible = "arm,cortex-a7";
64 operating-points-v2 = <&cpu0_opp_table>;
65 #cooling-cells = <2>; /* min followed by max */
66 enable-method = "psci";
71 compatible = "operating-points-v2";
72 opp-shared;
74 opp-408000000 {
75 opp-hz = /bits/ 64 <408000000>;
76 opp-microvolt = <950000>;
77 clock-latency-ns = <40000>;
78 opp-suspend;
80 opp-600000000 {
81 opp-hz = /bits/ 64 <600000000>;
82 opp-microvolt = <975000>;
84 opp-816000000 {
85 opp-hz = /bits/ 64 <816000000>;
86 opp-microvolt = <1000000>;
88 opp-1008000000 {
89 opp-hz = /bits/ 64 <1008000000>;
90 opp-microvolt = <1175000>;
92 opp-1200000000 {
93 opp-hz = /bits/ 64 <1200000000>;
94 opp-microvolt = <1275000>;
99 compatible = "simple-bus";
100 #address-cells = <1>;
101 #size-cells = <1>;
109 #dma-cells = <1>;
110 arm,pl330-periph-burst;
112 clock-names = "apb_pclk";
116 arm-pmu {
117 compatible = "arm,cortex-a7-pmu";
122 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
126 compatible = "arm,psci-1.0", "arm,psci-0.2";
131 compatible = "arm,armv7-timer";
132 arm,cpu-registers-not-fw-configured;
137 clock-frequency = <24000000>;
141 compatible = "fixed-clock";
142 clock-frequency = <24000000>;
143 clock-output-names = "xin24m";
144 #clock-cells = <0>;
147 display_subsystem: display-subsystem {
148 compatible = "rockchip,display-subsystem";
153 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
156 clock-names = "i2s_clk", "i2s_hclk";
159 dma-names = "tx", "rx";
160 pinctrl-names = "default";
161 pinctrl-0 = <&i2s1_bus>;
166 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
169 clock-names = "i2s_clk", "i2s_hclk";
172 dma-names = "tx", "rx";
177 compatible = "rockchip,rk3228-spdif";
181 clock-names = "mclk", "hclk";
183 dma-names = "tx";
184 pinctrl-names = "default";
185 pinctrl-0 = <&spdif_tx>;
190 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
193 clock-names = "i2s_clk", "i2s_hclk";
196 dma-names = "tx", "rx";
201 compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd";
203 #address-cells = <1>;
204 #size-cells = <1>;
206 io_domains: io-domains {
207 compatible = "rockchip,rk3228-io-voltage-domain";
211 u2phy0: usb2-phy@760 {
212 compatible = "rockchip,rk3228-usb2phy";
215 clock-names = "phyclk";
216 clock-output-names = "usb480m_phy0";
217 #clock-cells = <0>;
220 u2phy0_otg: otg-port {
224 interrupt-names = "otg-bvalid", "otg-id",
226 #phy-cells = <0>;
230 u2phy0_host: host-port {
232 interrupt-names = "linestate";
233 #phy-cells = <0>;
238 u2phy1: usb2-phy@800 {
239 compatible = "rockchip,rk3228-usb2phy";
242 clock-names = "phyclk";
243 clock-output-names = "usb480m_phy1";
244 #clock-cells = <0>;
247 u2phy1_otg: otg-port {
249 interrupt-names = "linestate";
250 #phy-cells = <0>;
254 u2phy1_host: host-port {
256 interrupt-names = "linestate";
257 #phy-cells = <0>;
264 compatible = "snps,dw-apb-uart";
267 clock-frequency = <24000000>;
269 clock-names = "baudclk", "apb_pclk";
270 pinctrl-names = "default";
271 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
272 reg-shift = <2>;
273 reg-io-width = <4>;
278 compatible = "snps,dw-apb-uart";
281 clock-frequency = <24000000>;
283 clock-names = "baudclk", "apb_pclk";
284 pinctrl-names = "default";
285 pinctrl-0 = <&uart1_xfer>;
286 reg-shift = <2>;
287 reg-io-width = <4>;
292 compatible = "snps,dw-apb-uart";
295 clock-frequency = <24000000>;
297 clock-names = "baudclk", "apb_pclk";
298 pinctrl-names = "default";
299 pinctrl-0 = <&uart2_xfer>;
300 reg-shift = <2>;
301 reg-io-width = <4>;
305 efuse: efuse@11040000 { label
306 compatible = "rockchip,rk3228-efuse";
309 clock-names = "pclk_efuse";
310 #address-cells = <1>;
311 #size-cells = <1>;
323 compatible = "rockchip,rk3228-i2c";
326 #address-cells = <1>;
327 #size-cells = <0>;
328 clock-names = "i2c";
330 pinctrl-names = "default";
331 pinctrl-0 = <&i2c0_xfer>;
336 compatible = "rockchip,rk3228-i2c";
339 #address-cells = <1>;
340 #size-cells = <0>;
341 clock-names = "i2c";
343 pinctrl-names = "default";
344 pinctrl-0 = <&i2c1_xfer>;
349 compatible = "rockchip,rk3228-i2c";
352 #address-cells = <1>;
353 #size-cells = <0>;
354 clock-names = "i2c";
356 pinctrl-names = "default";
357 pinctrl-0 = <&i2c2_xfer>;
362 compatible = "rockchip,rk3228-i2c";
365 #address-cells = <1>;
366 #size-cells = <0>;
367 clock-names = "i2c";
369 pinctrl-names = "default";
370 pinctrl-0 = <&i2c3_xfer>;
375 compatible = "rockchip,rk3228-spi";
378 #address-cells = <1>;
379 #size-cells = <0>;
381 clock-names = "spiclk", "apb_pclk";
382 pinctrl-names = "default";
383 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
388 compatible = "snps,dw-wdt";
396 compatible = "rockchip,rk3288-pwm";
398 #pwm-cells = <3>;
400 clock-names = "pwm";
401 pinctrl-names = "default";
402 pinctrl-0 = <&pwm0_pin>;
407 compatible = "rockchip,rk3288-pwm";
409 #pwm-cells = <3>;
411 clock-names = "pwm";
412 pinctrl-names = "default";
413 pinctrl-0 = <&pwm1_pin>;
418 compatible = "rockchip,rk3288-pwm";
420 #pwm-cells = <3>;
422 clock-names = "pwm";
423 pinctrl-names = "default";
424 pinctrl-0 = <&pwm2_pin>;
429 compatible = "rockchip,rk3288-pwm";
431 #pwm-cells = <2>;
433 clock-names = "pwm";
434 pinctrl-names = "default";
435 pinctrl-0 = <&pwm3_pin>;
440 compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
444 clock-names = "timer", "pclk";
447 cru: clock-controller@110e0000 {
448 compatible = "rockchip,rk3228-cru";
451 #clock-cells = <1>;
452 #reset-cells = <1>;
453 assigned-clocks =
459 assigned-clock-rates =
467 thermal-zones {
468 cpu_thermal: cpu-thermal {
469 polling-delay-passive = <100>; /* milliseconds */
470 polling-delay = <5000>; /* milliseconds */
472 thermal-sensors = <&tsadc 0>;
492 cooling-maps {
495 cooling-device =
503 cooling-device =
514 compatible = "rockchip,rk3228-tsadc";
518 clock-names = "tsadc", "apb_pclk";
519 assigned-clocks = <&cru SCLK_TSADC>;
520 assigned-clock-rates = <32768>;
522 reset-names = "tsadc-apb";
523 pinctrl-names = "init", "default", "sleep";
524 pinctrl-0 = <&otp_pin>;
525 pinctrl-1 = <&otp_out>;
526 pinctrl-2 = <&otp_pin>;
527 #thermal-sensor-cells = <0>;
528 rockchip,hw-tshut-temp = <95000>;
532 hdmi_phy: hdmi-phy@12030000 {
533 compatible = "rockchip,rk3228-hdmi-phy";
536 clock-names = "sysclk", "refoclk", "refpclk";
537 #clock-cells = <0>;
538 clock-output-names = "hdmiphy_phy";
539 #phy-cells = <0>;
544 compatible = "rockchip,rk3228-mali", "arm,mali-400";
552 interrupt-names = "gp",
559 clock-names = "bus", "core";
568 interrupt-names = "vpu_mmu";
570 clock-names = "aclk", "iface";
571 iommu-cells = <0>;
579 interrupt-names = "vdec_mmu";
581 clock-names = "aclk", "iface";
582 iommu-cells = <0>;
587 compatible = "rockchip,rk3228-vop";
591 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
593 reset-names = "axi", "ahb", "dclk";
598 #address-cells = <1>;
599 #size-cells = <0>;
603 remote-endpoint = <&hdmi_in_vop>;
612 interrupt-names = "vop_mmu";
614 clock-names = "aclk", "iface";
615 #iommu-cells = <0>;
620 compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga";
624 clock-names = "aclk", "hclk", "sclk";
626 reset-names = "core", "axi", "ahb";
633 interrupt-names = "iep_mmu";
635 clock-names = "aclk", "iface";
636 iommu-cells = <0>;
641 compatible = "rockchip,rk3228-dw-hdmi";
643 reg-io-width = <4>;
645 assigned-clocks = <&cru SCLK_HDMI_PHY>;
646 assigned-clock-parents = <&hdmi_phy>;
648 clock-names = "isfr", "iahb", "cec";
649 pinctrl-names = "default";
650 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
652 reset-names = "hdmi";
654 phy-names = "hdmi";
660 #address-cells = <1>;
661 #size-cells = <0>;
664 remote-endpoint = <&vop_out_hdmi>;
671 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
676 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
677 fifo-depth = <0x100>;
678 pinctrl-names = "default";
679 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
684 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
689 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
690 fifo-depth = <0x100>;
691 pinctrl-names = "default";
692 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
697 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
700 clock-frequency = <37500000>;
701 max-frequency = <37500000>;
704 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
705 bus-width = <8>;
706 rockchip,default-sample-phase = <158>;
707 fifo-depth = <0x100>;
708 pinctrl-names = "default";
709 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
711 reset-names = "reset";
716 compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb",
721 clock-names = "otg";
723 g-np-tx-fifo-size = <16>;
724 g-rx-fifo-size = <280>;
725 g-tx-fifo-size = <256 128 128 64 32 16>;
727 phy-names = "usb2-phy";
732 compatible = "generic-ehci";
737 phy-names = "usb";
742 compatible = "generic-ohci";
747 phy-names = "usb";
752 compatible = "generic-ehci";
757 phy-names = "usb";
762 compatible = "generic-ohci";
767 phy-names = "usb";
772 compatible = "generic-ehci";
777 phy-names = "usb";
782 compatible = "generic-ohci";
787 phy-names = "usb";
792 compatible = "rockchip,rk3228-gmac";
795 interrupt-names = "macirq";
800 clock-names = "stmmaceth", "mac_clk_rx",
805 reset-names = "stmmaceth";
810 gic: interrupt-controller@32010000 {
811 compatible = "arm,gic-400";
812 interrupt-controller;
813 #interrupt-cells = <3>;
814 #address-cells = <0>;
824 compatible = "rockchip,rk3228-pinctrl";
826 #address-cells = <1>;
827 #size-cells = <1>;
831 compatible = "rockchip,gpio-bank";
836 gpio-controller;
837 #gpio-cells = <2>;
839 interrupt-controller;
840 #interrupt-cells = <2>;
844 compatible = "rockchip,gpio-bank";
849 gpio-controller;
850 #gpio-cells = <2>;
852 interrupt-controller;
853 #interrupt-cells = <2>;
857 compatible = "rockchip,gpio-bank";
862 gpio-controller;
863 #gpio-cells = <2>;
865 interrupt-controller;
866 #interrupt-cells = <2>;
870 compatible = "rockchip,gpio-bank";
875 gpio-controller;
876 #gpio-cells = <2>;
878 interrupt-controller;
879 #interrupt-cells = <2>;
882 pcfg_pull_up: pcfg-pull-up {
883 bias-pull-up;
886 pcfg_pull_down: pcfg-pull-down {
887 bias-pull-down;
890 pcfg_pull_none: pcfg-pull-none {
891 bias-disable;
894 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
895 drive-strength = <12>;
899 sdmmc_clk: sdmmc-clk {
903 sdmmc_cmd: sdmmc-cmd {
907 sdmmc_bus4: sdmmc-bus4 {
916 sdio_clk: sdio-clk {
920 sdio_cmd: sdio-cmd {
924 sdio_bus4: sdio-bus4 {
933 emmc_clk: emmc-clk {
937 emmc_cmd: emmc-cmd {
941 emmc_bus8: emmc-bus8 {
954 rgmii_pins: rgmii-pins {
972 rmii_pins: rmii-pins {
985 phy_pins: phy-pins {
992 hdmi_hpd: hdmi-hpd {
996 hdmii2c_xfer: hdmii2c-xfer {
1001 hdmi_cec: hdmi-cec {
1007 i2c0_xfer: i2c0-xfer {
1014 i2c1_xfer: i2c1-xfer {
1021 i2c2_xfer: i2c2-xfer {
1028 i2c3_xfer: i2c3-xfer {
1035 spi0_clk: spi0-clk {
1038 spi0_cs0: spi0-cs0 {
1041 spi0_tx: spi0-tx {
1044 spi0_rx: spi0-rx {
1047 spi0_cs1: spi0-cs1 {
1053 spi1_clk: spi1-clk {
1056 spi1_cs0: spi1-cs0 {
1059 spi1_rx: spi1-rx {
1062 spi1_tx: spi1-tx {
1065 spi1_cs1: spi1-cs1 {
1071 i2s1_bus: i2s1-bus {
1085 pwm0_pin: pwm0-pin {
1091 pwm1_pin: pwm1-pin {
1097 pwm2_pin: pwm2-pin {
1103 pwm3_pin: pwm3-pin {
1109 spdif_tx: spdif-tx {
1115 otp_pin: otp-pin {
1119 otp_out: otp-out {
1125 uart0_xfer: uart0-xfer {
1130 uart0_cts: uart0-cts {
1134 uart0_rts: uart0-rts {
1140 uart1_xfer: uart1-xfer {
1145 uart1_cts: uart1-cts {
1149 uart1_rts: uart1-rts {
1155 uart2_xfer: uart2-xfer {
1160 uart21_xfer: uart21-xfer {
1165 uart2_cts: uart2-cts {
1169 uart2_rts: uart2-rts {