Lines Matching full:cru
7 #include <dt-bindings/clock/rk3228-cru.h>
31 resets = <&cru SRST_CORE0>;
35 clocks = <&cru ARMCLK>;
43 resets = <&cru SRST_CORE1>;
53 resets = <&cru SRST_CORE2>;
63 resets = <&cru SRST_CORE3>;
111 clocks = <&cru ACLK_DMAC>;
157 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
170 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
180 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
194 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
214 clocks = <&cru SCLK_OTGPHY0>;
241 clocks = <&cru SCLK_OTGPHY1>;
268 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
282 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
296 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
308 clocks = <&cru PCLK_EFUSE_256>;
329 clocks = <&cru PCLK_I2C0>;
342 clocks = <&cru PCLK_I2C1>;
355 clocks = <&cru PCLK_I2C2>;
368 clocks = <&cru PCLK_I2C3>;
380 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
391 clocks = <&cru PCLK_CPU>;
399 clocks = <&cru PCLK_PWM>;
410 clocks = <&cru PCLK_PWM>;
421 clocks = <&cru PCLK_PWM>;
432 clocks = <&cru PCLK_PWM>;
443 clocks = <&xin24m>, <&cru PCLK_TIMER>;
447 cru: clock-controller@110e0000 { label
448 compatible = "rockchip,rk3228-cru";
454 <&cru PLL_GPLL>, <&cru ARMCLK>,
455 <&cru PLL_CPLL>, <&cru ACLK_PERI>,
456 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
457 <&cru ACLK_CPU>, <&cru HCLK_CPU>,
458 <&cru PCLK_CPU>;
517 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
519 assigned-clocks = <&cru SCLK_TSADC>;
521 resets = <&cru SRST_TSADC>;
535 clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>;
558 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
560 resets = <&cru SRST_GPU_A>;
569 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
580 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
590 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
592 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
613 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
623 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
625 resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>;
634 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
645 assigned-clocks = <&cru SCLK_HDMI_PHY>;
647 clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_CEC>;
651 resets = <&cru SRST_HDMI_P>;
674 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
675 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
687 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
688 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
702 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
703 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
710 resets = <&cru SRST_EMMC>;
720 clocks = <&cru HCLK_OTG>;
735 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
745 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
755 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
765 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
775 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
785 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
796 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
797 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
798 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
799 <&cru PCLK_GMAC>;
804 resets = <&cru SRST_GMAC>;
834 clocks = <&cru PCLK_GPIO0>;
847 clocks = <&cru PCLK_GPIO1>;
860 clocks = <&cru PCLK_GPIO2>;
873 clocks = <&cru PCLK_GPIO3>;