Lines Matching +full:rk3066 +full:- +full:smp
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3066a-cru.h>
10 #include <dt-bindings/power/rk3066-power.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
19 enable-method = "rockchip,rk3066-smp";
23 compatible = "arm,cortex-a9";
24 next-level-cache = <&L2>;
26 operating-points = <
36 clock-latency = <40000>;
41 compatible = "arm,cortex-a9";
42 next-level-cache = <&L2>;
47 display-subsystem {
48 compatible = "rockchip,display-subsystem";
53 compatible = "mmio-sram";
55 #address-cells = <1>;
56 #size-cells = <1>;
59 smp-sram@0 {
60 compatible = "rockchip,rk3066-smp-sram";
66 compatible = "rockchip,rk3066-vop";
72 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
73 power-domains = <&power RK3066_PD_VIO>;
77 reset-names = "axi", "ahb", "dclk";
81 #address-cells = <1>;
82 #size-cells = <0>;
86 remote-endpoint = <&hdmi_in_vop0>;
92 compatible = "rockchip,rk3066-vop";
98 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
99 power-domains = <&power RK3066_PD_VIO>;
103 reset-names = "axi", "ahb", "dclk";
107 #address-cells = <1>;
108 #size-cells = <0>;
112 remote-endpoint = <&hdmi_in_vop1>;
118 compatible = "rockchip,rk3066-hdmi";
122 clock-names = "hclk";
123 pinctrl-names = "default";
124 pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>;
125 power-domains = <&power RK3066_PD_VIO>;
130 #address-cells = <1>;
131 #size-cells = <0>;
135 #address-cells = <1>;
136 #size-cells = <0>;
140 remote-endpoint = <&vop0_out_hdmi>;
145 remote-endpoint = <&vop1_out_hdmi>;
156 compatible = "rockchip,rk3066-i2s";
159 pinctrl-names = "default";
160 pinctrl-0 = <&i2s0_bus>;
162 clock-names = "i2s_clk", "i2s_hclk";
164 dma-names = "tx", "rx";
165 rockchip,playback-channels = <8>;
166 rockchip,capture-channels = <2>;
167 #sound-dai-cells = <0>;
172 compatible = "rockchip,rk3066-i2s";
175 pinctrl-names = "default";
176 pinctrl-0 = <&i2s1_bus>;
178 clock-names = "i2s_clk", "i2s_hclk";
180 dma-names = "tx", "rx";
181 rockchip,playback-channels = <2>;
182 rockchip,capture-channels = <2>;
183 #sound-dai-cells = <0>;
188 compatible = "rockchip,rk3066-i2s";
191 pinctrl-names = "default";
192 pinctrl-0 = <&i2s2_bus>;
194 clock-names = "i2s_clk", "i2s_hclk";
196 dma-names = "tx", "rx";
197 rockchip,playback-channels = <2>;
198 rockchip,capture-channels = <2>;
199 #sound-dai-cells = <0>;
203 cru: clock-controller@20000000 {
204 compatible = "rockchip,rk3066a-cru";
208 #clock-cells = <1>;
209 #reset-cells = <1>;
210 assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,
214 assigned-clock-rates = <400000000>, <594000000>,
221 compatible = "snps,dw-apb-timer-osc";
225 clock-names = "timer", "pclk";
229 compatible = "rockchip,rk3066a-efuse";
231 #address-cells = <1>;
232 #size-cells = <1>;
234 clock-names = "pclk_efuse";
242 compatible = "snps,dw-apb-timer-osc";
246 clock-names = "timer", "pclk";
250 compatible = "snps,dw-apb-timer-osc";
254 clock-names = "timer", "pclk";
258 compatible = "rockchip,rk3066-tsadc";
261 clock-names = "saradc", "apb_pclk";
263 #io-channel-cells = <1>;
265 reset-names = "saradc-apb";
270 compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy";
272 #address-cells = <1>;
273 #size-cells = <0>;
276 usbphy0: usb-phy@17c {
277 #phy-cells = <0>;
280 clock-names = "phyclk";
281 #clock-cells = <0>;
284 usbphy1: usb-phy@188 {
285 #phy-cells = <0>;
288 clock-names = "phyclk";
289 #clock-cells = <0>;
294 compatible = "rockchip,rk3066a-pinctrl";
296 #address-cells = <1>;
297 #size-cells = <1>;
301 compatible = "rockchip,gpio-bank";
306 gpio-controller;
307 #gpio-cells = <2>;
309 interrupt-controller;
310 #interrupt-cells = <2>;
314 compatible = "rockchip,gpio-bank";
319 gpio-controller;
320 #gpio-cells = <2>;
322 interrupt-controller;
323 #interrupt-cells = <2>;
327 compatible = "rockchip,gpio-bank";
332 gpio-controller;
333 #gpio-cells = <2>;
335 interrupt-controller;
336 #interrupt-cells = <2>;
340 compatible = "rockchip,gpio-bank";
345 gpio-controller;
346 #gpio-cells = <2>;
348 interrupt-controller;
349 #interrupt-cells = <2>;
353 compatible = "rockchip,gpio-bank";
358 gpio-controller;
359 #gpio-cells = <2>;
361 interrupt-controller;
362 #interrupt-cells = <2>;
366 compatible = "rockchip,gpio-bank";
371 gpio-controller;
372 #gpio-cells = <2>;
374 interrupt-controller;
375 #interrupt-cells = <2>;
379 bias-pull-pin-default;
383 bias-disable;
387 emac_xfer: emac-xfer {
398 emac_mdio: emac-mdio {
405 emmc_clk: emmc-clk {
409 emmc_cmd: emmc-cmd {
413 emmc_rst: emmc-rst {
421 * flash/emmc is the boot-device.
426 hdmi_hpd: hdmi-hpd {
430 hdmii2c_xfer: hdmii2c-xfer {
437 i2c0_xfer: i2c0-xfer {
444 i2c1_xfer: i2c1-xfer {
451 i2c2_xfer: i2c2-xfer {
458 i2c3_xfer: i2c3-xfer {
465 i2c4_xfer: i2c4-xfer {
472 pwm0_out: pwm0-out {
478 pwm1_out: pwm1-out {
484 pwm2_out: pwm2-out {
490 pwm3_out: pwm3-out {
496 spi0_clk: spi0-clk {
499 spi0_cs0: spi0-cs0 {
502 spi0_tx: spi0-tx {
505 spi0_rx: spi0-rx {
508 spi0_cs1: spi0-cs1 {
514 spi1_clk: spi1-clk {
517 spi1_cs0: spi1-cs0 {
520 spi1_rx: spi1-rx {
523 spi1_tx: spi1-tx {
526 spi1_cs1: spi1-cs1 {
532 uart0_xfer: uart0-xfer {
537 uart0_cts: uart0-cts {
541 uart0_rts: uart0-rts {
547 uart1_xfer: uart1-xfer {
552 uart1_cts: uart1-cts {
556 uart1_rts: uart1-rts {
562 uart2_xfer: uart2-xfer {
570 uart3_xfer: uart3-xfer {
575 uart3_cts: uart3-cts {
579 uart3_rts: uart3-rts {
585 sd0_clk: sd0-clk {
589 sd0_cmd: sd0-cmd {
593 sd0_cd: sd0-cd {
597 sd0_wp: sd0-wp {
601 sd0_bus1: sd0-bus-width1 {
605 sd0_bus4: sd0-bus-width4 {
614 sd1_clk: sd1-clk {
618 sd1_cmd: sd1-cmd {
622 sd1_cd: sd1-cd {
626 sd1_wp: sd1-wp {
630 sd1_bus1: sd1-bus-width1 {
634 sd1_bus4: sd1-bus-width4 {
643 i2s0_bus: i2s0-bus {
657 i2s1_bus: i2s1-bus {
668 i2s2_bus: i2s2-bus {
681 compatible = "rockchip,rk3066-mali", "arm,mali-400";
692 interrupt-names = "gp",
702 power-domains = <&power RK3066_PD_GPU>;
706 pinctrl-names = "default";
707 pinctrl-0 = <&i2c0_xfer>;
711 pinctrl-names = "default";
712 pinctrl-0 = <&i2c1_xfer>;
716 pinctrl-names = "default";
717 pinctrl-0 = <&i2c2_xfer>;
721 pinctrl-names = "default";
722 pinctrl-0 = <&i2c3_xfer>;
726 pinctrl-names = "default";
727 pinctrl-0 = <&i2c4_xfer>;
731 clock-frequency = <50000000>;
733 dma-names = "rx-tx";
734 max-frequency = <50000000>;
735 pinctrl-names = "default";
736 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
741 dma-names = "rx-tx";
742 pinctrl-names = "default";
743 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
748 dma-names = "rx-tx";
752 power: power-controller {
753 compatible = "rockchip,rk3066-power-controller";
754 #power-domain-cells = <1>;
755 #address-cells = <1>;
756 #size-cells = <0>;
803 pinctrl-names = "default";
804 pinctrl-0 = <&pwm0_out>;
808 pinctrl-names = "default";
809 pinctrl-0 = <&pwm1_out>;
813 pinctrl-names = "default";
814 pinctrl-0 = <&pwm2_out>;
818 pinctrl-names = "default";
819 pinctrl-0 = <&pwm3_out>;
823 pinctrl-names = "default";
824 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
828 pinctrl-names = "default";
829 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
833 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
835 dma-names = "tx", "rx";
836 pinctrl-names = "default";
837 pinctrl-0 = <&uart0_xfer>;
841 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
843 dma-names = "tx", "rx";
844 pinctrl-names = "default";
845 pinctrl-0 = <&uart1_xfer>;
849 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
851 dma-names = "tx", "rx";
852 pinctrl-names = "default";
853 pinctrl-0 = <&uart2_xfer>;
857 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
859 dma-names = "tx", "rx";
860 pinctrl-names = "default";
861 pinctrl-0 = <&uart3_xfer>;
865 compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
869 compatible = "rockchip,rk3066-emac";