Lines Matching full:cru
9 #include <dt-bindings/clock/rk3066a-cru.h>
37 clocks = <&cru ARMCLK>;
69 clocks = <&cru ACLK_LCDC0>,
70 <&cru DCLK_LCDC0>,
71 <&cru HCLK_LCDC0>;
74 resets = <&cru SRST_LCDC0_AXI>,
75 <&cru SRST_LCDC0_AHB>,
76 <&cru SRST_LCDC0_DCLK>;
95 clocks = <&cru ACLK_LCDC1>,
96 <&cru DCLK_LCDC1>,
97 <&cru HCLK_LCDC1>;
100 resets = <&cru SRST_LCDC1_AXI>,
101 <&cru SRST_LCDC1_AHB>,
102 <&cru SRST_LCDC1_DCLK>;
121 clocks = <&cru HCLK_HDMI>;
161 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
177 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
193 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
203 cru: clock-controller@20000000 { label
204 compatible = "rockchip,rk3066a-cru";
210 assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,
211 <&cru ACLK_CPU>, <&cru HCLK_CPU>,
212 <&cru PCLK_CPU>, <&cru ACLK_PERI>,
213 <&cru HCLK_PERI>, <&cru PCLK_PERI>;
224 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
233 clocks = <&cru PCLK_EFUSE>;
245 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
253 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
260 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
264 resets = <&cru SRST_TSADC>;
279 clocks = <&cru SCLK_OTGPHY0>;
287 clocks = <&cru SCLK_OTGPHY1>;
304 clocks = <&cru PCLK_GPIO0>;
317 clocks = <&cru PCLK_GPIO1>;
330 clocks = <&cru PCLK_GPIO2>;
343 clocks = <&cru PCLK_GPIO3>;
356 clocks = <&cru PCLK_GPIO4>;
369 clocks = <&cru PCLK_GPIO6>;
760 clocks = <&cru ACLK_LCDC0>,
761 <&cru ACLK_LCDC1>,
762 <&cru DCLK_LCDC0>,
763 <&cru DCLK_LCDC1>,
764 <&cru HCLK_LCDC0>,
765 <&cru HCLK_LCDC1>,
766 <&cru SCLK_CIF1>,
767 <&cru ACLK_CIF1>,
768 <&cru HCLK_CIF1>,
769 <&cru SCLK_CIF0>,
770 <&cru ACLK_CIF0>,
771 <&cru HCLK_CIF0>,
772 <&cru HCLK_HDMI>,
773 <&cru ACLK_IPP>,
774 <&cru HCLK_IPP>,
775 <&cru ACLK_RGA>,
776 <&cru HCLK_RGA>;
787 clocks = <&cru ACLK_VDPU>,
788 <&cru ACLK_VEPU>,
789 <&cru HCLK_VDPU>,
790 <&cru HCLK_VEPU>;
796 clocks = <&cru ACLK_GPU>;