Lines Matching +full:rk3066 +full:- +full:smp
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h>
8 #include <dt-bindings/soc/rockchip,boot-mode.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
16 interrupt-parent = <&gic>;
32 #address-cells = <1>;
33 #size-cells = <0>;
34 enable-method = "rockchip,rk3036-smp";
38 compatible = "arm,cortex-a7";
41 operating-points = <
45 clock-latency = <40000>;
51 compatible = "arm,cortex-a7";
58 compatible = "simple-bus";
59 #address-cells = <1>;
60 #size-cells = <1>;
68 #dma-cells = <1>;
69 arm,pl330-broken-no-flushp;
70 arm,pl330-periph-burst;
72 clock-names = "apb_pclk";
76 arm-pmu {
77 compatible = "arm,cortex-a7-pmu";
80 interrupt-affinity = <&cpu0>, <&cpu1>;
83 display-subsystem {
84 compatible = "rockchip,display-subsystem";
89 compatible = "arm,armv7-timer";
90 arm,cpu-registers-not-fw-configured;
95 clock-frequency = <24000000>;
99 compatible = "fixed-clock";
100 clock-frequency = <24000000>;
101 clock-output-names = "xin24m";
102 #clock-cells = <0>;
106 compatible = "mmio-sram";
108 #address-cells = <1>;
109 #size-cells = <1>;
112 smp-sram@0 {
113 compatible = "rockchip,rk3066-smp-sram";
119 compatible = "rockchip,rk3036-mali", "arm,mali-400";
125 interrupt-names = "gp",
129 assigned-clocks = <&cru SCLK_GPU>;
130 assigned-clock-rates = <100000000>;
132 clock-names = "bus", "core";
138 compatible = "rockchip,rk3036-vop";
142 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
144 reset-names = "axi", "ahb", "dclk";
149 #address-cells = <1>;
150 #size-cells = <0>;
153 remote-endpoint = <&hdmi_in_vop>;
162 interrupt-names = "vop_mmu";
164 clock-names = "aclk", "iface";
165 #iommu-cells = <0>;
169 gic: interrupt-controller@10139000 {
170 compatible = "arm,gic-400";
171 interrupt-controller;
172 #interrupt-cells = <3>;
173 #address-cells = <0>;
183 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
188 clock-names = "otg";
190 g-np-tx-fifo-size = <16>;
191 g-rx-fifo-size = <275>;
192 g-tx-fifo-size = <256 128 128 64 64 32>;
197 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
202 clock-names = "otg";
208 compatible = "rockchip,rk3036-emac", "snps,arc-emac";
211 #address-cells = <1>;
212 #size-cells = <0>;
215 clock-names = "hclk", "macref", "macclk";
221 assigned-clocks = <&cru SCLK_MACPLL>;
222 assigned-clock-parents = <&cru PLL_DPLL>;
223 max-speed = <100>;
224 phy-mode = "rmii";
229 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
231 clock-frequency = <37500000>;
232 max-frequency = <37500000>;
234 clock-names = "biu", "ciu";
235 fifo-depth = <0x100>;
238 reset-names = "reset";
243 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
245 max-frequency = <37500000>;
248 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
249 fifo-depth = <0x100>;
252 reset-names = "reset";
257 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
260 bus-width = <8>;
261 cap-mmc-highspeed;
262 clock-frequency = <37500000>;
263 max-frequency = <37500000>;
266 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
267 rockchip,default-sample-phase = <158>;
268 disable-wp;
270 dma-names = "rx-tx";
271 fifo-depth = <0x100>;
272 mmc-ddr-1_8v;
273 non-removable;
274 pinctrl-names = "default";
275 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
277 reset-names = "reset";
282 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
285 clock-names = "i2s_clk", "i2s_hclk";
288 dma-names = "tx", "rx";
289 pinctrl-names = "default";
290 pinctrl-0 = <&i2s_bus>;
291 #sound-dai-cells = <0>;
295 cru: clock-controller@20000000 {
296 compatible = "rockchip,rk3036-cru";
299 #clock-cells = <1>;
300 #reset-cells = <1>;
301 assigned-clocks = <&cru PLL_GPLL>;
302 assigned-clock-rates = <594000000>;
306 compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
309 reboot-mode {
310 compatible = "syscon-reboot-mode";
312 mode-normal = <BOOT_NORMAL>;
313 mode-recovery = <BOOT_RECOVERY>;
314 mode-bootloader = <BOOT_FASTBOOT>;
315 mode-loader = <BOOT_BL_DOWNLOAD>;
319 acodec: acodec-ana@20030000 {
320 compatible = "rk3036-codec";
323 clock-names = "acodec_pclk";
329 compatible = "rockchip,rk3036-inno-hdmi";
333 clock-names = "pclk";
335 pinctrl-names = "default";
336 pinctrl-0 = <&hdmi_ctl>;
340 #address-cells = <1>;
341 #size-cells = <0>;
344 remote-endpoint = <&vop_out_hdmi>;
350 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
354 clock-names = "timer", "pclk";
358 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
360 #pwm-cells = <3>;
362 clock-names = "pwm";
363 pinctrl-names = "default";
364 pinctrl-0 = <&pwm0_pin>;
369 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
371 #pwm-cells = <3>;
373 clock-names = "pwm";
374 pinctrl-names = "default";
375 pinctrl-0 = <&pwm1_pin>;
380 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
382 #pwm-cells = <3>;
384 clock-names = "pwm";
385 pinctrl-names = "default";
386 pinctrl-0 = <&pwm2_pin>;
391 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
393 #pwm-cells = <2>;
395 clock-names = "pwm";
396 pinctrl-names = "default";
397 pinctrl-0 = <&pwm3_pin>;
402 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
405 #address-cells = <1>;
406 #size-cells = <0>;
407 clock-names = "i2c";
409 pinctrl-names = "default";
410 pinctrl-0 = <&i2c1_xfer>;
415 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
418 #address-cells = <1>;
419 #size-cells = <0>;
420 clock-names = "i2c";
422 pinctrl-names = "default";
423 pinctrl-0 = <&i2c2_xfer>;
428 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
431 reg-shift = <2>;
432 reg-io-width = <4>;
433 clock-frequency = <24000000>;
435 clock-names = "baudclk", "apb_pclk";
436 pinctrl-names = "default";
437 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
442 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
445 reg-shift = <2>;
446 reg-io-width = <4>;
447 clock-frequency = <24000000>;
449 clock-names = "baudclk", "apb_pclk";
450 pinctrl-names = "default";
451 pinctrl-0 = <&uart1_xfer>;
456 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
459 reg-shift = <2>;
460 reg-io-width = <4>;
461 clock-frequency = <24000000>;
463 clock-names = "baudclk", "apb_pclk";
464 pinctrl-names = "default";
465 pinctrl-0 = <&uart2_xfer>;
470 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
473 #address-cells = <1>;
474 #size-cells = <0>;
475 clock-names = "i2c";
477 pinctrl-names = "default";
478 pinctrl-0 = <&i2c0_xfer>;
483 compatible = "rockchip,rockchip-spi";
487 clock-names = "apb-pclk","spi_pclk";
489 dma-names = "tx", "rx";
490 pinctrl-names = "default";
491 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
492 #address-cells = <1>;
493 #size-cells = <0>;
498 compatible = "rockchip,rk3036-pinctrl";
500 #address-cells = <1>;
501 #size-cells = <1>;
505 compatible = "rockchip,gpio-bank";
510 gpio-controller;
511 #gpio-cells = <2>;
513 interrupt-controller;
514 #interrupt-cells = <2>;
518 compatible = "rockchip,gpio-bank";
523 gpio-controller;
524 #gpio-cells = <2>;
526 interrupt-controller;
527 #interrupt-cells = <2>;
531 compatible = "rockchip,gpio-bank";
536 gpio-controller;
537 #gpio-cells = <2>;
539 interrupt-controller;
540 #interrupt-cells = <2>;
544 bias-pull-pin-default;
547 pcfg_pull_none: pcfg-pull-none {
548 bias-disable;
552 pwm0_pin: pwm0-pin {
558 pwm1_pin: pwm1-pin {
564 pwm2_pin: pwm2-pin {
570 pwm3_pin: pwm3-pin {
576 sdmmc_clk: sdmmc-clk {
580 sdmmc_cmd: sdmmc-cmd {
584 sdmmc_cd: sdmmc-cd {
588 sdmmc_bus1: sdmmc-bus1 {
592 sdmmc_bus4: sdmmc-bus4 {
601 sdio_bus1: sdio-bus1 {
605 sdio_bus4: sdio-bus4 {
612 sdio_cmd: sdio-cmd {
616 sdio_clk: sdio-clk {
626 emmc_clk: emmc-clk {
630 emmc_cmd: emmc-cmd {
634 emmc_bus8: emmc-bus8 {
647 emac_xfer: emac-xfer {
658 emac_mdio: emac-mdio {
665 i2c0_xfer: i2c0-xfer {
672 i2c1_xfer: i2c1-xfer {
679 i2c2_xfer: i2c2-xfer {
686 i2s_bus: i2s-bus {
697 hdmi_ctl: hdmi-ctl {
706 uart0_xfer: uart0-xfer {
711 uart0_cts: uart0-cts {
715 uart0_rts: uart0-rts {
721 uart1_xfer: uart1-xfer {
729 uart2_xfer: uart2-xfer {
736 spi-pins {
737 spi_txd:spi-txd {
741 spi_rxd:spi-rxd {
745 spi_clk:spi-clk {
749 spi_cs0:spi-cs0 {
754 spi_cs1:spi-cs1 {