Lines Matching +full:intc +full:- +full:irqpin
1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car M1A (R8A77781) SoC
14 #include <dt-bindings/clock/r8a7778-clock.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/interrupt-controller/irq.h>
20 interrupt-parent = <&gic>;
21 #address-cells = <1>;
22 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
30 compatible = "arm,cortex-a9";
32 clock-frequency = <800000000>;
44 compatible = "simple-bus";
45 #address-cells = <1>;
46 #size-cells = <1>;
51 compatible = "renesas,ether-r8a7778",
52 "renesas,rcar-gen1-ether";
56 power-domains = <&cpg_clocks>;
57 phy-mode = "rmii";
58 #address-cells = <1>;
59 #size-cells = <0>;
63 gic: interrupt-controller@fe438000 {
65 #interrupt-cells = <3>;
66 interrupt-controller;
71 /* irqpin: IRQ0 - IRQ3 */
72 irqpin: interrupt-controller@fe78001c { label
73 compatible = "renesas,intc-irqpin-r8a7778", "renesas,intc-irqpin";
74 #interrupt-cells = <2>;
75 interrupt-controller;
87 sense-bitfield-width = <2>;
91 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
94 #gpio-cells = <2>;
95 gpio-controller;
96 gpio-ranges = <&pfc 0 0 32>;
97 #interrupt-cells = <2>;
98 interrupt-controller;
102 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
105 #gpio-cells = <2>;
106 gpio-controller;
107 gpio-ranges = <&pfc 0 32 32>;
108 #interrupt-cells = <2>;
109 interrupt-controller;
113 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
116 #gpio-cells = <2>;
117 gpio-controller;
118 gpio-ranges = <&pfc 0 64 32>;
119 #interrupt-cells = <2>;
120 interrupt-controller;
124 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
127 #gpio-cells = <2>;
128 gpio-controller;
129 gpio-ranges = <&pfc 0 96 32>;
130 #interrupt-cells = <2>;
131 interrupt-controller;
135 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
138 #gpio-cells = <2>;
139 gpio-controller;
140 gpio-ranges = <&pfc 0 128 27>;
141 #interrupt-cells = <2>;
142 interrupt-controller;
146 compatible = "renesas,pfc-r8a7778";
151 #address-cells = <1>;
152 #size-cells = <0>;
153 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
157 power-domains = <&cpg_clocks>;
162 #address-cells = <1>;
163 #size-cells = <0>;
164 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
168 power-domains = <&cpg_clocks>;
173 #address-cells = <1>;
174 #size-cells = <0>;
175 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
179 power-domains = <&cpg_clocks>;
184 #address-cells = <1>;
185 #size-cells = <0>;
186 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
190 power-domains = <&cpg_clocks>;
195 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
201 clock-names = "fck";
202 power-domains = <&cpg_clocks>;
210 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
216 clock-names = "fck";
217 power-domains = <&cpg_clocks>;
225 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
231 clock-names = "fck";
232 power-domains = <&cpg_clocks>;
241 * #sound-dai-cells is required
243 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
244 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
246 compatible = "renesas,rcar_sound-r8a7778", "renesas,rcar_sound-gen1";
270 clock-names = "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4",
279 src3: src-3 { };
280 src4: src-4 { };
281 src5: src-5 { };
282 src6: src-6 { };
283 src7: src-7 { };
284 src8: src-8 { };
285 src9: src-9 { };
289 ssi3: ssi-3 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
290 ssi4: ssi-4 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
291 ssi5: ssi-5 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
292 ssi6: ssi-6 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
293 ssi7: ssi-7 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
294 ssi8: ssi-8 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
295 ssi9: ssi-9 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
300 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
306 clock-names = "fck", "brg_int", "scif_clk";
307 power-domains = <&cpg_clocks>;
312 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
318 clock-names = "fck", "brg_int", "scif_clk";
319 power-domains = <&cpg_clocks>;
324 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
330 clock-names = "fck", "brg_int", "scif_clk";
331 power-domains = <&cpg_clocks>;
336 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
342 clock-names = "fck", "brg_int", "scif_clk";
343 power-domains = <&cpg_clocks>;
348 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
354 clock-names = "fck", "brg_int", "scif_clk";
355 power-domains = <&cpg_clocks>;
360 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
366 clock-names = "fck", "brg_int", "scif_clk";
367 power-domains = <&cpg_clocks>;
372 compatible = "renesas,hscif-r8a7778",
373 "renesas,rcar-gen1-hscif", "renesas,hscif";
378 clock-names = "fck", "brg_int", "scif_clk";
379 power-domains = <&cpg_clocks>;
384 compatible = "renesas,hscif-r8a7778",
385 "renesas,rcar-gen1-hscif", "renesas,hscif";
390 clock-names = "fck", "brg_int", "scif_clk";
391 power-domains = <&cpg_clocks>;
396 compatible = "renesas,mmcif-r8a7778", "renesas,sh-mmcif";
400 power-domains = <&cpg_clocks>;
405 compatible = "renesas,sdhi-r8a7778",
406 "renesas,rcar-gen1-sdhi";
410 power-domains = <&cpg_clocks>;
415 compatible = "renesas,sdhi-r8a7778",
416 "renesas,rcar-gen1-sdhi";
420 power-domains = <&cpg_clocks>;
425 compatible = "renesas,sdhi-r8a7778",
426 "renesas,rcar-gen1-sdhi";
430 power-domains = <&cpg_clocks>;
435 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
439 power-domains = <&cpg_clocks>;
440 #address-cells = <1>;
441 #size-cells = <0>;
446 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
450 power-domains = <&cpg_clocks>;
451 #address-cells = <1>;
452 #size-cells = <0>;
457 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
461 power-domains = <&cpg_clocks>;
462 #address-cells = <1>;
463 #size-cells = <0>;
468 #address-cells = <1>;
469 #size-cells = <1>;
474 compatible = "fixed-clock";
475 #clock-cells = <0>;
476 clock-frequency = <0>;
481 compatible = "fixed-clock";
482 #clock-cells = <0>;
484 clock-frequency = <0>;
489 compatible = "renesas,r8a7778-cpg-clocks";
491 #clock-cells = <1>;
493 clock-output-names = "plla", "pllb", "b",
495 #power-domain-cells = <0>;
500 compatible = "fixed-clock";
501 #clock-cells = <0>;
502 clock-frequency = <0>;
505 compatible = "fixed-clock";
506 #clock-cells = <0>;
507 clock-frequency = <0>;
510 compatible = "fixed-clock";
511 #clock-cells = <0>;
512 clock-frequency = <0>;
517 compatible = "fixed-factor-clock";
519 #clock-cells = <0>;
520 clock-div = <12>;
521 clock-mult = <1>;
524 compatible = "fixed-factor-clock";
526 #clock-cells = <0>;
527 clock-div = <1>;
528 clock-mult = <1>;
531 compatible = "fixed-factor-clock";
533 #clock-cells = <0>;
534 clock-div = <4>;
535 clock-mult = <1>;
538 compatible = "fixed-factor-clock";
540 #clock-cells = <0>;
541 clock-div = <8>;
542 clock-mult = <1>;
545 compatible = "fixed-factor-clock";
547 #clock-cells = <0>;
548 clock-div = <1>;
549 clock-mult = <1>;
554 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
577 #clock-cells = <1>;
578 clock-indices = <
591 clock-output-names =
599 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
605 #clock-cells = <1>;
606 clock-indices = <
610 clock-output-names =
614 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
625 #clock-cells = <1>;
626 clock-indices = <
633 clock-output-names =
638 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
649 #clock-cells = <1>;
650 clock-indices = <
657 clock-output-names =
658 "sru-src0", "sru-src1", "sru-src2",
659 "sru-src3", "sru-src4", "sru-src5",
660 "sru-src6", "sru-src7", "sru-src8";
664 rst: reset-controller@ffcc0000 {
665 compatible = "renesas,r8a7778-reset-wdt";