Lines Matching +full:tpu +full:- +full:r8a7740
1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Mobile A1 (R8A77400) SoC
8 #include <dt-bindings/clock/r8a7740-clock.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 compatible = "renesas,r8a7740";
14 interrupt-parent = <&gic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
19 #address-cells = <1>;
20 #size-cells = <0>;
22 compatible = "arm,cortex-a9";
25 clock-frequency = <800000000>;
26 power-domains = <&pd_a3sm>;
27 next-level-cache = <&L2>;
31 gic: interrupt-controller@c2800000 {
33 #interrupt-cells = <3>;
34 interrupt-controller;
39 L2: cache-controller@f0100000 {
40 compatible = "arm,pl310-cache";
43 power-domains = <&pd_a3sm>;
44 arm,data-latency = <3 3 3>;
45 arm,tag-latency = <2 2 2>;
46 arm,shared-override;
47 cache-unified;
48 cache-level = <2>;
51 dbsc3: memory-controller@fe400000 {
52 compatible = "renesas,dbsc3-r8a7740";
54 power-domains = <&pd_a4s>;
58 compatible = "arm,cortex-a9-pmu";
63 compatible = "arm,coresight-etm3x";
64 power-domains = <&pd_d4>;
69 compatible = "renesas,r8a7740-ceu";
72 power-domains = <&pd_a4r>;
78 compatible = "renesas,r8a7740-ceu";
81 power-domains = <&pd_a4r>;
86 compatible = "renesas,r8a7740-cmt1";
90 clock-names = "fck";
91 power-domains = <&pd_c5>;
95 /* irqpin0: IRQ0 - IRQ7 */
96 irqpin0: interrupt-controller@e6900000 {
97 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
98 #interrupt-cells = <2>;
99 interrupt-controller;
114 power-domains = <&pd_a4s>;
117 /* irqpin1: IRQ8 - IRQ15 */
118 irqpin1: interrupt-controller@e6900004 {
119 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
120 #interrupt-cells = <2>;
121 interrupt-controller;
136 power-domains = <&pd_a4s>;
139 /* irqpin2: IRQ16 - IRQ23 */
140 irqpin2: interrupt-controller@e6900008 {
141 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
142 #interrupt-cells = <2>;
143 interrupt-controller;
158 power-domains = <&pd_a4s>;
161 /* irqpin3: IRQ24 - IRQ31 */
162 irqpin3: interrupt-controller@e690000c {
163 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
164 #interrupt-cells = <2>;
165 interrupt-controller;
180 power-domains = <&pd_a4s>;
184 compatible = "renesas,gether-r8a7740";
189 power-domains = <&pd_a4s>;
190 phy-mode = "mii";
191 #address-cells = <1>;
192 #size-cells = <0>;
197 #address-cells = <1>;
198 #size-cells = <0>;
199 compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
206 power-domains = <&pd_a4r>;
211 #address-cells = <1>;
212 #size-cells = <0>;
213 compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
220 power-domains = <&pd_a3sp>;
225 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
229 clock-names = "fck";
230 power-domains = <&pd_a3sp>;
235 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
239 clock-names = "fck";
240 power-domains = <&pd_a3sp>;
245 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
249 clock-names = "fck";
250 power-domains = <&pd_a3sp>;
255 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
259 clock-names = "fck";
260 power-domains = <&pd_a3sp>;
265 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
269 clock-names = "fck";
270 power-domains = <&pd_a3sp>;
275 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
279 clock-names = "fck";
280 power-domains = <&pd_a3sp>;
285 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
289 clock-names = "fck";
290 power-domains = <&pd_a3sp>;
295 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
299 clock-names = "fck";
300 power-domains = <&pd_a3sp>;
305 compatible = "renesas,scifb-r8a7740", "renesas,scifb";
309 clock-names = "fck";
310 power-domains = <&pd_a3sp>;
315 compatible = "renesas,pfc-r8a7740";
318 gpio-controller;
319 #gpio-cells = <2>;
320 gpio-ranges = <&pfc 0 0 212>;
321 interrupts-extended =
330 power-domains = <&pd_c5>;
333 tpu: pwm@e6600000 { label
334 compatible = "renesas,tpu-r8a7740", "renesas,tpu";
337 power-domains = <&pd_a3sp>;
339 #pwm-cells = <3>;
343 compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif";
348 power-domains = <&pd_a3sp>;
353 compatible = "renesas,sdhi-r8a7740";
359 power-domains = <&pd_a3sp>;
360 cap-sd-highspeed;
361 cap-sdio-irq;
366 compatible = "renesas,sdhi-r8a7740";
372 power-domains = <&pd_a3sp>;
373 cap-sd-highspeed;
374 cap-sdio-irq;
379 compatible = "renesas,sdhi-r8a7740";
385 power-domains = <&pd_a3sp>;
386 cap-sd-highspeed;
387 cap-sdio-irq;
392 #sound-dai-cells = <1>;
393 compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2";
397 power-domains = <&pd_a4mp>;
402 compatible = "renesas,tmu-r8a7740", "renesas,tmu";
408 clock-names = "fck";
409 power-domains = <&pd_a4r>;
417 compatible = "renesas,tmu-r8a7740", "renesas,tmu";
423 clock-names = "fck";
424 power-domains = <&pd_a4r>;
432 #address-cells = <1>;
433 #size-cells = <1>;
438 compatible = "fixed-clock";
439 #clock-cells = <0>;
440 clock-frequency = <32768>;
443 compatible = "fixed-clock";
444 #clock-cells = <0>;
445 clock-frequency = <0>;
448 compatible = "fixed-clock";
449 #clock-cells = <0>;
450 clock-frequency = <0>;
453 compatible = "fixed-clock";
454 #clock-cells = <0>;
455 clock-frequency = <27000000>;
458 compatible = "fixed-clock";
459 #clock-cells = <0>;
460 clock-frequency = <0>;
463 compatible = "fixed-clock";
464 #clock-cells = <0>;
465 clock-frequency = <0>;
468 compatible = "fixed-clock";
469 #clock-cells = <0>;
470 clock-frequency = <0>;
473 compatible = "fixed-clock";
474 #clock-cells = <0>;
475 clock-frequency = <0>;
480 compatible = "renesas,r8a7740-cpg-clocks";
483 #clock-cells = <1>;
484 clock-output-names = "system", "pllc0", "pllc1",
494 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
500 #clock-cells = <0>;
503 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
509 #clock-cells = <0>;
512 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
515 #clock-cells = <0>;
518 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
521 #clock-cells = <0>;
524 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
527 #clock-cells = <0>;
530 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
534 #clock-cells = <0>;
537 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
541 #clock-cells = <0>;
544 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
548 #clock-cells = <0>;
551 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
554 #clock-cells = <0>;
559 compatible = "fixed-factor-clock";
561 #clock-cells = <0>;
562 clock-div = <2>;
563 clock-mult = <1>;
566 compatible = "fixed-factor-clock";
568 #clock-cells = <0>;
569 clock-div = <2>;
570 clock-mult = <1>;
575 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
578 #clock-cells = <1>;
579 clock-indices = <
582 clock-output-names =
586 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
593 #clock-cells = <1>;
594 clock-indices = <
599 clock-output-names =
604 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
614 #clock-cells = <1>;
615 clock-indices = <
625 clock-output-names =
632 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
643 #clock-cells = <1>;
644 clock-indices = <
649 clock-output-names =
654 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
660 #clock-cells = <1>;
661 clock-indices = <
665 clock-output-names =
670 sysc: system-controller@e6180000 {
671 compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile";
674 pm-domains {
676 #address-cells = <1>;
677 #size-cells = <0>;
678 #power-domain-cells = <0>;
682 #power-domain-cells = <0>;
687 #power-domain-cells = <0>;
692 #power-domain-cells = <0>;
697 #address-cells = <1>;
698 #size-cells = <0>;
699 #power-domain-cells = <0>;
703 #power-domain-cells = <0>;
709 #address-cells = <1>;
710 #size-cells = <0>;
711 #power-domain-cells = <0>;
715 #power-domain-cells = <0>;
720 #power-domain-cells = <0>;
725 #power-domain-cells = <0>;
731 #power-domain-cells = <0>;