Lines Matching +full:0 +full:xe6550000
21 #size-cells = <0>;
23 cpu0: cpu@0 {
26 reg = <0>;
33 L2_CA15: cache-controller-0 {
65 reg = <0 0xe6790000 0 0x10000>;
71 reg = <0 0xe67a0000 0 0x10000>;
86 reg = <0 0xe6700020 0 0x89e0>;
121 #size-cells = <0>;
123 reg = <0 0xe60b0000 0 0x428>;
133 reg = <0 0xe6130000 0 0x1004>;
152 reg = <0 0xe61c0000 0 0x200>;
153 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
193 reg = <0 0xe61c0200 0 0x200>;
226 reg = <0 0xe6050000 0 0x9000>;
230 <&pfc 0 0 31>, <&pfc 32 32 9>,
237 <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>,
238 <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>,
239 <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
240 <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
241 <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
242 <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
243 <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
244 <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
245 <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>,
246 <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>,
247 <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
248 <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
249 <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
250 <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
251 <&irqc1 24 0>, <&irqc1 25 0>;
257 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
258 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
266 #size-cells = <0>;
268 reg = <0 0xe6500000 0 0x428>;
277 #size-cells = <0>;
279 reg = <0 0xe6510000 0 0x428>;
288 #size-cells = <0>;
290 reg = <0 0xe6520000 0 0x428>;
299 #size-cells = <0>;
301 reg = <0 0xe6530000 0 0x428>;
310 #size-cells = <0>;
312 reg = <0 0xe6540000 0 0x428>;
321 #size-cells = <0>;
323 reg = <0 0xe6550000 0 0x428>;
332 #size-cells = <0>;
334 reg = <0 0xe6560000 0 0x428>;
343 #size-cells = <0>;
345 reg = <0 0xe6570000 0 0x428>;
354 reg = <0 0xe6c20000 0 0x100>;
364 reg = <0 0xe6c30000 0 0x100>;
374 reg = <0 0xe6c40000 0 0x100>;
384 reg = <0 0xe6c50000 0 0x100>;
394 reg = <0 0xe6ce0000 0 0x100>;
404 reg = <0 0xe6cf0000 0 0x100>;
414 reg = <0 0xee100000 0 0x100>;
424 reg = <0 0xee120000 0 0x100>;
434 reg = <0 0xee140000 0 0x100>;
444 reg = <0 0xee200000 0 0x80>;
454 reg = <0 0xee220000 0 0x80>;
465 #address-cells = <0>;
467 reg = <0 0xf1001000 0 0x1000>,
468 <0 0xf1002000 0 0x2000>,
469 <0 0xf1004000 0 0x2000>,
470 <0 0xf1006000 0 0x2000>;
482 ranges = <0 0 0 0x20000000>;
483 reg = <0 0xfec10000 0 0x400>;
496 #clock-cells = <0>;
501 #clock-cells = <0>;
506 #clock-cells = <0>;
511 #clock-cells = <0>;
513 clock-frequency = <0>;
517 #clock-cells = <0>;
519 clock-frequency = <0>;
525 reg = <0 0xe6150000 0 0x10000>;
537 reg = <0 0xe6150010 0 4>;
538 clocks = <&pll1_div2_clk>, <0>,
539 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
540 #clock-cells = <0>;
545 reg = <0 0xe6150074 0 4>;
547 <0>, <&extal2_clk>;
548 #clock-cells = <0>;
552 reg = <0 0xe6150078 0 4>;
554 <0>, <&extal2_clk>;
555 #clock-cells = <0>;
559 reg = <0 0xe615007c 0 4>;
561 <0>, <&extal2_clk>;
562 #clock-cells = <0>;
566 reg = <0 0xe6150240 0 4>;
568 <0>, <&extal2_clk>;
569 #clock-cells = <0>;
573 reg = <0 0xe6150244 0 4>;
575 <0>, <&extal2_clk>;
576 #clock-cells = <0>;
580 reg = <0 0xe6150008 0 4>;
582 <0>, <&extal2_clk>, <&main_div2_clk>,
583 <&extalr_clk>, <0>, <0>;
584 #clock-cells = <0>;
588 reg = <0 0xe615000c 0 4>;
590 <0>, <&extal2_clk>, <&main_div2_clk>,
591 <&extalr_clk>, <0>, <0>;
592 #clock-cells = <0>;
596 reg = <0 0xe615001c 0 4>;
598 <0>, <&extal2_clk>, <&main_div2_clk>,
599 <&extalr_clk>, <0>, <0>;
600 #clock-cells = <0>;
604 reg = <0 0xe6150014 0 4>;
606 <0>, <&extal2_clk>, <&main_div2_clk>,
607 <&extalr_clk>, <0>, <0>;
608 #clock-cells = <0>;
612 reg = <0 0xe6150034 0 4>;
614 <0>, <&extal2_clk>, <&main_div2_clk>,
615 <&extalr_clk>, <0>, <0>;
616 #clock-cells = <0>;
620 reg = <0 0xe6150018 0 4>;
622 <&fsiack_clk>, <0>;
623 #clock-cells = <0>;
627 reg = <0 0xe6150090 0 4>;
629 <&fsibck_clk>, <0>;
630 #clock-cells = <0>;
634 reg = <0 0xe6150080 0 4>;
637 #clock-cells = <0>;
641 reg = <0 0xe6150098 0 4>;
643 #clock-cells = <0>;
647 reg = <0 0xe615026c 0 4>;
649 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
650 #clock-cells = <0>;
654 reg = <0 0xe6150094 0 4>;
657 #clock-cells = <0>;
664 #clock-cells = <0>;
671 #clock-cells = <0>;
678 #clock-cells = <0>;
685 #clock-cells = <0>;
693 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
709 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
732 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
748 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
761 reg = <0 0xff000044 0 4>;
766 reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>;
771 #size-cells = <0>;
772 #power-domain-cells = <0>;
774 pd_c4: c4@0 {
775 reg = <0>;
777 #size-cells = <0>;
778 #power-domain-cells = <0>;
782 #power-domain-cells = <0>;
787 #power-domain-cells = <0>;
793 #size-cells = <0>;
794 #power-domain-cells = <0>;
798 #power-domain-cells = <0>;
805 #size-cells = <0>;
806 #power-domain-cells = <0>;
810 #power-domain-cells = <0>;
817 #size-cells = <0>;
818 #power-domain-cells = <0>;
822 #power-domain-cells = <0>;
829 #power-domain-cells = <0>;
834 #power-domain-cells = <0>;
839 #power-domain-cells = <0>;
845 #size-cells = <0>;
846 #power-domain-cells = <0>;
850 #power-domain-cells = <0>;
856 #power-domain-cells = <0>;
861 #power-domain-cells = <0>;
867 #size-cells = <0>;
868 #power-domain-cells = <0>;
872 #power-domain-cells = <0>;
877 #power-domain-cells = <0>;
883 #power-domain-cells = <0>;
889 #size-cells = <0>;
890 #power-domain-cells = <0>;
894 #power-domain-cells = <0>;
899 #power-domain-cells = <0>;