Lines Matching refs:gcc
5 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
8 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
245 clocks = <&gcc GSBI2_H_CLK>;
259 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
269 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
283 clocks = <&gcc GSBI4_H_CLK>;
297 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
307 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
320 clocks = <&gcc GSBI5_H_CLK>;
334 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
344 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
357 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
371 clocks = <&gcc GSBI7_H_CLK>;
383 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
393 clocks = <&gcc SATA_PHY_CFG_CLK>;
406 clocks = <&gcc SFAB_SATA_S_H_CLK>,
407 <&gcc SATA_H_CLK>,
408 <&gcc SATA_A_CLK>,
409 <&gcc SATA_RXOOB_CLK>,
410 <&gcc SATA_PMALIVE_CLK>;
414 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
435 gcc: clock-controller@900000 { label
436 compatible = "qcom,gcc-ipq8064";
480 clocks = <&gcc PCIE_A_CLK>,
481 <&gcc PCIE_H_CLK>,
482 <&gcc PCIE_PHY_CLK>,
483 <&gcc PCIE_AUX_CLK>,
484 <&gcc PCIE_ALT_REF_CLK>;
487 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
490 resets = <&gcc PCIE_ACLK_RESET>,
491 <&gcc PCIE_HCLK_RESET>,
492 <&gcc PCIE_POR_RESET>,
493 <&gcc PCIE_PCI_RESET>,
494 <&gcc PCIE_PHY_RESET>,
495 <&gcc PCIE_EXT_RESET>;
531 clocks = <&gcc PCIE_1_A_CLK>,
532 <&gcc PCIE_1_H_CLK>,
533 <&gcc PCIE_1_PHY_CLK>,
534 <&gcc PCIE_1_AUX_CLK>,
535 <&gcc PCIE_1_ALT_REF_CLK>;
538 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
541 resets = <&gcc PCIE_1_ACLK_RESET>,
542 <&gcc PCIE_1_HCLK_RESET>,
543 <&gcc PCIE_1_POR_RESET>,
544 <&gcc PCIE_1_PCI_RESET>,
545 <&gcc PCIE_1_PHY_RESET>,
546 <&gcc PCIE_1_EXT_RESET>;
582 clocks = <&gcc PCIE_2_A_CLK>,
583 <&gcc PCIE_2_H_CLK>,
584 <&gcc PCIE_2_PHY_CLK>,
585 <&gcc PCIE_2_AUX_CLK>,
586 <&gcc PCIE_2_ALT_REF_CLK>;
589 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
592 resets = <&gcc PCIE_2_ACLK_RESET>,
593 <&gcc PCIE_2_HCLK_RESET>,
594 <&gcc PCIE_2_POR_RESET>,
595 <&gcc PCIE_2_PCI_RESET>,
596 <&gcc PCIE_2_PHY_RESET>,
597 <&gcc PCIE_2_EXT_RESET>;
637 clocks = <&gcc GMAC_CORE1_CLK>;
640 resets = <&gcc GMAC_CORE1_RESET>;
660 clocks = <&gcc GMAC_CORE2_CLK>;
663 resets = <&gcc GMAC_CORE2_RESET>;
683 clocks = <&gcc GMAC_CORE3_CLK>;
686 resets = <&gcc GMAC_CORE3_RESET>;
706 clocks = <&gcc GMAC_CORE4_CLK>;
709 resets = <&gcc GMAC_CORE4_RESET>;
727 clocks = <&gcc SDC1_H_CLK>;
737 clocks = <&gcc SDC3_H_CLK>;
756 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
776 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;