Lines Matching +full:kpss +full:- +full:acc +full:- +full:v2
1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
18 interrupt-parent = <&intc>;
20 reserved-memory {
21 #address-cells = <0x1>;
22 #size-cells = <0x1>;
27 no-map;
32 no-map;
44 #address-cells = <1>;
45 #size-cells = <0>;
48 compatible = "arm,cortex-a7";
49 enable-method = "qcom,kpss-acc-v2";
50 next-level-cache = <&L2>;
51 qcom,acc = <&acc0>;
55 clock-frequency = <0>;
56 clock-latency = <256000>;
57 operating-points-v2 = <&cpu0_opp_table>;
62 compatible = "arm,cortex-a7";
63 enable-method = "qcom,kpss-acc-v2";
64 next-level-cache = <&L2>;
65 qcom,acc = <&acc1>;
69 clock-frequency = <0>;
70 clock-latency = <256000>;
71 operating-points-v2 = <&cpu0_opp_table>;
76 compatible = "arm,cortex-a7";
77 enable-method = "qcom,kpss-acc-v2";
78 next-level-cache = <&L2>;
79 qcom,acc = <&acc2>;
83 clock-frequency = <0>;
84 clock-latency = <256000>;
85 operating-points-v2 = <&cpu0_opp_table>;
90 compatible = "arm,cortex-a7";
91 enable-method = "qcom,kpss-acc-v2";
92 next-level-cache = <&L2>;
93 qcom,acc = <&acc3>;
97 clock-frequency = <0>;
98 clock-latency = <256000>;
99 operating-points-v2 = <&cpu0_opp_table>;
102 L2: l2-cache {
104 cache-level = <2>;
110 compatible = "operating-points-v2";
111 opp-shared;
113 opp-48000000 {
114 opp-hz = /bits/ 64 <48000000>;
115 clock-latency-ns = <256000>;
117 opp-200000000 {
118 opp-hz = /bits/ 64 <200000000>;
119 clock-latency-ns = <256000>;
121 opp-500000000 {
122 opp-hz = /bits/ 64 <500000000>;
123 clock-latency-ns = <256000>;
125 opp-716000000 {
126 opp-hz = /bits/ 64 <716000000>;
127 clock-latency-ns = <256000>;
137 compatible = "arm,cortex-a7-pmu";
144 compatible = "fixed-clock";
145 clock-frequency = <32768>;
146 #clock-cells = <0>;
150 compatible = "fixed-clock";
151 clock-frequency = <48000000>;
152 #clock-cells = <0>;
158 compatible = "qcom,scm-ipq4019";
163 compatible = "arm,armv7-timer";
168 clock-frequency = <48000000>;
169 always-on;
173 #address-cells = <1>;
174 #size-cells = <1>;
176 compatible = "simple-bus";
178 intc: interrupt-controller@b000000 {
179 compatible = "qcom,msm-qgic2";
180 interrupt-controller;
181 #interrupt-cells = <3>;
186 gcc: clock-controller@1800000 {
187 compatible = "qcom,gcc-ipq4019";
188 #clock-cells = <1>;
189 #reset-cells = <1>;
197 clock-names = "core";
202 compatible = "qcom,ipq4019-pinctrl";
204 gpio-controller;
205 gpio-ranges = <&tlmm 0 0 100>;
206 #gpio-cells = <2>;
207 interrupt-controller;
208 #interrupt-cells = <2>;
213 compatible = "qcom,sdhci-msm-v4";
216 interrupt-names = "hc_irq", "pwr_irq";
217 bus-width = <8>;
220 clock-names = "core", "iface", "xo";
225 compatible = "qcom,bam-v1.7.0";
229 clock-names = "bam_clk";
230 #dma-cells = <1>;
236 compatible = "qcom,spi-qup-v2.2.1";
241 clock-names = "core", "iface";
242 #address-cells = <1>;
243 #size-cells = <0>;
245 dma-names = "rx", "tx";
250 compatible = "qcom,spi-qup-v2.2.1";
255 clock-names = "core", "iface";
256 #address-cells = <1>;
257 #size-cells = <0>;
259 dma-names = "rx", "tx";
264 compatible = "qcom,i2c-qup-v2.2.1";
269 clock-names = "iface", "core";
270 #address-cells = <1>;
271 #size-cells = <0>;
273 dma-names = "rx", "tx";
278 compatible = "qcom,i2c-qup-v2.2.1";
283 clock-names = "iface", "core";
284 #address-cells = <1>;
285 #size-cells = <0>;
287 dma-names = "rx", "tx";
292 compatible = "qcom,bam-v1.7.0";
296 clock-names = "bam_clk";
297 #dma-cells = <1>;
299 qcom,controlled-remotely;
304 compatible = "qcom,crypto-v5.1";
309 clock-names = "iface", "bus", "core";
311 dma-names = "rx", "tx";
315 acc0: clock-controller@b088000 {
316 compatible = "qcom,kpss-acc-v2";
320 acc1: clock-controller@b098000 {
321 compatible = "qcom,kpss-acc-v2";
325 acc2: clock-controller@b0a8000 {
326 compatible = "qcom,kpss-acc-v2";
330 acc3: clock-controller@b0b8000 {
331 compatible = "qcom,kpss-acc-v2";
366 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
372 clock-names = "core", "iface";
374 dma-names = "rx", "tx";
378 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
384 clock-names = "core", "iface";
386 dma-names = "rx", "tx";
390 compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019";
393 timeout-sec = <10>;
403 compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
408 reg-names = "dbi", "elbi", "parf", "config";
410 linux,pci-domain = <0>;
411 bus-range = <0x00 0xff>;
412 num-lanes = <1>;
413 #address-cells = <3>;
414 #size-cells = <2>;
420 interrupt-names = "msi";
421 #interrupt-cells = <1>;
422 interrupt-map-mask = <0 0 0 0x7>;
423 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
430 clock-names = "aux",
446 reset-names = "axi_m",
463 compatible = "qcom,bam-v1.7.0";
467 clock-names = "bam_clk";
468 #dma-cells = <1>;
473 nand: qpic-nand@79b0000 {
474 compatible = "qcom,ipq4019-nand";
476 #address-cells = <1>;
477 #size-cells = <0>;
480 clock-names = "core", "aon";
485 dma-names = "tx", "rx", "cmd";
491 nand-ecc-strength = <4>;
492 nand-ecc-step-size = <512>;
493 nand-bus-width = <8>;
498 compatible = "qcom,ipq4019-wifi";
506 reset-names = "wifi_cpu_init", "wifi_radio_srif",
512 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
531 interrupt-names = "msi0", "msi1", "msi2", "msi3",
540 compatible = "qcom,ipq4019-wifi";
548 reset-names = "wifi_cpu_init", "wifi_radio_srif",
554 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
573 interrupt-names = "msi0", "msi1", "msi2", "msi3",
582 #address-cells = <1>;
583 #size-cells = <0>;
584 compatible = "qcom,ipq4019-mdio";
588 ethphy0: ethernet-phy@0 {
592 ethphy1: ethernet-phy@1 {
596 ethphy2: ethernet-phy@2 {
600 ethphy3: ethernet-phy@3 {
604 ethphy4: ethernet-phy@4 {