Lines Matching refs:gcc
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
108 thermal-sensors = <&gcc 7>;
129 thermal-sensors = <&gcc 8>;
150 thermal-sensors = <&gcc 9>;
171 thermal-sensors = <&gcc 10>;
442 clocks = <&gcc GSBI1_H_CLK>;
455 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
467 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
481 clocks = <&gcc GSBI2_H_CLK>;
496 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
509 clocks = <&gcc GSBI3_H_CLK>;
521 clocks = <&gcc GSBI3_QUP_CLK>,
522 <&gcc GSBI3_H_CLK>;
535 clocks = <&gcc GSBI4_H_CLK>;
548 clocks = <&gcc GSBI4_QUP_CLK>,
549 <&gcc GSBI4_H_CLK>;
560 clocks = <&gcc GSBI5_H_CLK>;
571 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
583 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
596 clocks = <&gcc GSBI6_H_CLK>;
607 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
619 clocks = <&gcc GSBI6_QUP_CLK>,
620 <&gcc GSBI6_H_CLK>;
631 clocks = <&gcc GSBI7_H_CLK>;
643 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
655 clocks = <&gcc GSBI7_QUP_CLK>,
656 <&gcc GSBI7_H_CLK>;
665 clocks = <&gcc PRNG_CLK>;
823 gcc: clock-controller@900000 { label
824 compatible = "qcom,gcc-apq8064";
927 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
929 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
931 resets = <&gcc USB_HS1_RESET>;
958 clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>;
960 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
962 resets = <&gcc USB_HS3_RESET>;
989 clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>;
991 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
993 resets = <&gcc USB_HS4_RESET>;
1020 clocks = <&gcc SATA_PHY_CFG_CLK>;
1031 clocks = <&gcc SFAB_SATA_S_H_CLK>,
1032 <&gcc SATA_H_CLK>,
1033 <&gcc SATA_A_CLK>,
1034 <&gcc SATA_RXOOB_CLK>,
1035 <&gcc SATA_PMALIVE_CLK>;
1042 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
1043 <&gcc SATA_PMALIVE_CLK>;
1056 clocks = <&gcc SDC1_H_CLK>;
1066 clocks = <&gcc SDC3_H_CLK>;
1076 clocks = <&gcc SDC4_H_CLK>;
1096 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1114 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1132 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1400 clocks = <&gcc PCIE_A_CLK>,
1401 <&gcc PCIE_H_CLK>,
1402 <&gcc PCIE_PHY_REF_CLK>;
1404 resets = <&gcc PCIE_ACLK_RESET>,
1405 <&gcc PCIE_HCLK_RESET>,
1406 <&gcc PCIE_POR_RESET>,
1407 <&gcc PCIE_PCI_RESET>,
1408 <&gcc PCIE_PHY_RESET>;