Lines Matching +full:smd +full:- +full:rpm
1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/soc/qcom,gsbi.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
16 interrupt-parent = <&intc>;
18 reserved-memory {
19 #address-cells = <1>;
20 #size-cells = <1>;
25 no-map;
30 no-map;
35 #address-cells = <1>;
36 #size-cells = <0>;
40 enable-method = "qcom,kpss-acc-v1";
43 next-level-cache = <&L2>;
46 cpu-idle-states = <&CPU_SPC>;
51 enable-method = "qcom,kpss-acc-v1";
54 next-level-cache = <&L2>;
57 cpu-idle-states = <&CPU_SPC>;
62 enable-method = "qcom,kpss-acc-v1";
65 next-level-cache = <&L2>;
68 cpu-idle-states = <&CPU_SPC>;
73 enable-method = "qcom,kpss-acc-v1";
76 next-level-cache = <&L2>;
79 cpu-idle-states = <&CPU_SPC>;
82 L2: l2-cache {
84 cache-level = <2>;
87 idle-states {
89 compatible = "qcom,idle-state-spc",
90 "arm,idle-state";
91 entry-latency-us = <400>;
92 exit-latency-us = <900>;
93 min-residency-us = <3000>;
103 thermal-zones {
104 cpu-thermal0 {
105 polling-delay-passive = <250>;
106 polling-delay = <1000>;
108 thermal-sensors = <&gcc 7>;
125 cpu-thermal1 {
126 polling-delay-passive = <250>;
127 polling-delay = <1000>;
129 thermal-sensors = <&gcc 8>;
146 cpu-thermal2 {
147 polling-delay-passive = <250>;
148 polling-delay = <1000>;
150 thermal-sensors = <&gcc 9>;
167 cpu-thermal3 {
168 polling-delay-passive = <250>;
169 polling-delay = <1000>;
171 thermal-sensors = <&gcc 10>;
189 cpu-pmu {
190 compatible = "qcom,krait-pmu";
196 compatible = "fixed-clock";
197 #clock-cells = <0>;
198 clock-frequency = <19200000>;
202 compatible = "fixed-clock";
203 #clock-cells = <0>;
204 clock-frequency = <27000000>;
208 compatible = "fixed-clock";
209 #clock-cells = <0>;
210 clock-frequency = <32768>;
215 compatible = "qcom,sfpb-mutex";
217 #hwlock-cells = <1>;
222 memory-region = <&smem_region>;
227 smd {
228 compatible = "qcom,smd";
234 qcom,smd-edge = <0>;
243 qcom,smd-edge = <1>;
252 qcom,smd-edge = <3>;
261 qcom,smd-edge = <6>;
270 #address-cells = <1>;
271 #size-cells = <0>;
273 qcom,ipc-1 = <&l2cc 8 4>;
274 qcom,ipc-2 = <&l2cc 8 14>;
275 qcom,ipc-3 = <&l2cc 8 23>;
276 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
280 #qcom,smem-state-cells = <1>;
287 interrupt-controller;
288 #interrupt-cells = <2>;
295 interrupt-controller;
296 #interrupt-cells = <2>;
303 interrupt-controller;
304 #interrupt-cells = <2>;
311 interrupt-controller;
312 #interrupt-cells = <2>;
318 compatible = "qcom,scm-apq8064";
321 clock-names = "core";
328 * That is why the ADC is referred to as "HKADC" - HouseKeeping
331 iio-hwmon {
332 compatible = "iio-hwmon";
333 io-channels = <&xoadc 0x00 0x01>, /* Battery */
343 #address-cells = <1>;
344 #size-cells = <1>;
346 compatible = "simple-bus";
349 compatible = "qcom,apq8064-pinctrl";
352 gpio-controller;
353 gpio-ranges = <&tlmm_pinmux 0 0 90>;
354 #gpio-cells = <2>;
355 interrupt-controller;
356 #interrupt-cells = <2>;
359 pinctrl-names = "default";
360 pinctrl-0 = <&ps_hold>;
368 intc: interrupt-controller@2000000 {
369 compatible = "qcom,msm-qgic2";
370 interrupt-controller;
371 #interrupt-cells = <3>;
377 compatible = "qcom,kpss-timer",
378 "qcom,kpss-wdt-apq8064", "qcom,msm-timer";
383 clock-frequency = <27000000>,
385 cpu-offset = <0x80000>;
388 acc0: clock-controller@2088000 {
389 compatible = "qcom,kpss-acc-v1";
393 acc1: clock-controller@2098000 {
394 compatible = "qcom,kpss-acc-v1";
398 acc2: clock-controller@20a8000 {
399 compatible = "qcom,kpss-acc-v1";
403 acc3: clock-controller@20b8000 {
404 compatible = "qcom,kpss-acc-v1";
408 saw0: power-controller@2089000 {
409 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
414 saw1: power-controller@2099000 {
415 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
420 saw2: power-controller@20a9000 {
421 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
426 saw3: power-controller@20b9000 {
427 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
432 sps_sic_non_secure: sps-sic-non-secure@12100000 {
439 compatible = "qcom,gsbi-v1.0.0";
440 cell-index = <1>;
443 clock-names = "iface";
444 #address-cells = <1>;
445 #size-cells = <1>;
448 syscon-tcsr = <&tcsr>;
451 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
456 clock-names = "core", "iface";
461 compatible = "qcom,i2c-qup-v1.1.1";
462 pinctrl-0 = <&i2c1_pins>;
463 pinctrl-1 = <&i2c1_pins_sleep>;
464 pinctrl-names = "default", "sleep";
468 clock-names = "core", "iface";
469 #address-cells = <1>;
470 #size-cells = <0>;
478 compatible = "qcom,gsbi-v1.0.0";
479 cell-index = <2>;
482 clock-names = "iface";
483 #address-cells = <1>;
484 #size-cells = <1>;
487 syscon-tcsr = <&tcsr>;
490 compatible = "qcom,i2c-qup-v1.1.1";
492 pinctrl-0 = <&i2c2_pins>;
493 pinctrl-1 = <&i2c2_pins_sleep>;
494 pinctrl-names = "default", "sleep";
497 clock-names = "core", "iface";
498 #address-cells = <1>;
499 #size-cells = <0>;
506 compatible = "qcom,gsbi-v1.0.0";
507 cell-index = <3>;
510 clock-names = "iface";
511 #address-cells = <1>;
512 #size-cells = <1>;
515 compatible = "qcom,i2c-qup-v1.1.1";
516 pinctrl-0 = <&i2c3_pins>;
517 pinctrl-1 = <&i2c3_pins_sleep>;
518 pinctrl-names = "default", "sleep";
523 clock-names = "core", "iface";
524 #address-cells = <1>;
525 #size-cells = <0>;
532 compatible = "qcom,gsbi-v1.0.0";
533 cell-index = <4>;
536 clock-names = "iface";
537 #address-cells = <1>;
538 #size-cells = <1>;
542 compatible = "qcom,i2c-qup-v1.1.1";
543 pinctrl-0 = <&i2c4_pins>;
544 pinctrl-1 = <&i2c4_pins_sleep>;
545 pinctrl-names = "default", "sleep";
550 clock-names = "core", "iface";
557 compatible = "qcom,gsbi-v1.0.0";
558 cell-index = <5>;
561 clock-names = "iface";
562 #address-cells = <1>;
563 #size-cells = <1>;
567 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
572 clock-names = "core", "iface";
577 compatible = "qcom,spi-qup-v1.1.1";
580 pinctrl-0 = <&spi5_default>;
581 pinctrl-1 = <&spi5_sleep>;
582 pinctrl-names = "default", "sleep";
584 clock-names = "core", "iface";
586 #address-cells = <1>;
587 #size-cells = <0>;
593 compatible = "qcom,gsbi-v1.0.0";
594 cell-index = <6>;
597 clock-names = "iface";
598 #address-cells = <1>;
599 #size-cells = <1>;
603 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
608 clock-names = "core", "iface";
613 compatible = "qcom,i2c-qup-v1.1.1";
614 pinctrl-0 = <&i2c6_pins>;
615 pinctrl-1 = <&i2c6_pins_sleep>;
616 pinctrl-names = "default", "sleep";
621 clock-names = "core", "iface";
628 compatible = "qcom,gsbi-v1.0.0";
629 cell-index = <7>;
632 clock-names = "iface";
633 #address-cells = <1>;
634 #size-cells = <1>;
636 syscon-tcsr = <&tcsr>;
639 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
644 clock-names = "core", "iface";
649 compatible = "qcom,i2c-qup-v1.1.1";
650 pinctrl-0 = <&i2c7_pins>;
651 pinctrl-1 = <&i2c7_pins_sleep>;
652 pinctrl-names = "default", "sleep";
657 clock-names = "core", "iface";
666 clock-names = "core";
672 qcom,controller-type = "pmic-arbiter";
676 interrupt-parent = <&tlmm_pinmux>;
678 #interrupt-cells = <2>;
679 interrupt-controller;
680 #address-cells = <1>;
681 #size-cells = <0>;
684 compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp";
690 gpio-controller;
691 #gpio-cells = <2>;
699 qcom,controller-type = "pmic-arbiter";
703 interrupt-parent = <&tlmm_pinmux>;
705 #interrupt-cells = <2>;
706 interrupt-controller;
707 #address-cells = <1>;
708 #size-cells = <0>;
712 compatible = "qcom,pm8921-gpio",
713 "qcom,ssbi-gpio";
715 interrupt-controller;
716 #interrupt-cells = <2>;
717 gpio-controller;
718 gpio-ranges = <&pm8921_gpio 0 0 44>;
719 #gpio-cells = <2>;
724 compatible = "qcom,pm8921-mpp",
725 "qcom,ssbi-mpp";
727 gpio-controller;
728 #gpio-cells = <2>;
745 compatible = "qcom,pm8921-rtc";
746 interrupt-parent = <&pmicintc>;
749 allow-set-time;
753 compatible = "qcom,pm8921-pwrkey";
755 interrupt-parent = <&pmicintc>;
758 pull-up;
762 compatible = "qcom,pm8921-adc";
764 interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>;
765 #address-cells = <2>;
766 #size-cells = <0>;
767 #io-channel-cells = <2>;
769 vcoin: adc-channel@00 {
772 vbat: adc-channel@01 {
775 dcin: adc-channel@02 {
778 vph_pwr: adc-channel@04 {
781 batt_therm: adc-channel@08 {
784 batt_id: adc-channel@09 {
787 usb_vbus: adc-channel@0a {
790 die_temp: adc-channel@0b {
793 ref_625mv: adc-channel@0c {
796 ref_1250mv: adc-channel@0d {
799 chg_temp: adc-channel@0e {
802 ref_muxoff: adc-channel@0f {
812 #address-cells = <1>;
813 #size-cells = <1>;
823 gcc: clock-controller@900000 {
824 compatible = "qcom,gcc-apq8064";
826 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
827 nvmem-cell-names = "calib", "calib_backup";
828 #clock-cells = <1>;
829 #reset-cells = <1>;
830 #thermal-sensor-cells = <1>;
833 lcc: clock-controller@28000000 {
834 compatible = "qcom,lcc-apq8064";
836 #clock-cells = <1>;
837 #reset-cells = <1>;
840 mmcc: clock-controller@4000000 {
841 compatible = "qcom,mmcc-apq8064";
843 #clock-cells = <1>;
844 #reset-cells = <1>;
847 l2cc: clock-controller@2011000 {
852 rpm@108000 {
853 compatible = "qcom,rpm-apq8064";
860 interrupt-names = "ack", "err", "wakeup";
862 rpmcc: clock-controller {
863 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
864 #clock-cells = <1>;
868 compatible = "qcom,rpm-pm8921-regulators";
912 pm8921_usb_switch: usb-switch {};
914 pm8921_hdmi_switch: hdmi-switch {
915 bias-pull-down;
923 compatible = "qcom,ci-hdrc";
928 clock-names = "core", "iface";
929 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
930 assigned-clock-rates = <60000000>;
932 reset-names = "core";
934 ahb-burst-config = <0>;
936 phy-names = "usb-phy";
938 #reset-cells = <1>;
942 compatible = "qcom,usb-hs-phy-apq8064",
943 "qcom,usb-hs-phy";
945 clock-names = "sleep", "ref";
947 reset-names = "por";
948 #phy-cells = <0>;
954 compatible = "qcom,ci-hdrc";
959 clock-names = "core", "iface";
960 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
961 assigned-clock-rates = <60000000>;
963 reset-names = "core";
965 ahb-burst-config = <0>;
967 phy-names = "usb-phy";
969 #reset-cells = <1>;
973 compatible = "qcom,usb-hs-phy-apq8064",
974 "qcom,usb-hs-phy";
975 #phy-cells = <0>;
977 clock-names = "sleep", "ref";
979 reset-names = "por";
985 compatible = "qcom,ci-hdrc";
990 clock-names = "core", "iface";
991 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
992 assigned-clock-rates = <60000000>;
994 reset-names = "core";
996 ahb-burst-config = <0>;
998 phy-names = "usb-phy";
1000 #reset-cells = <1>;
1004 compatible = "qcom,usb-hs-phy-apq8064",
1005 "qcom,usb-hs-phy";
1006 #phy-cells = <0>;
1008 clock-names = "sleep", "ref";
1010 reset-names = "por";
1016 compatible = "qcom,apq8064-sata-phy";
1019 reg-names = "phy_mem";
1021 clock-names = "cfg";
1022 #phy-cells = <0>;
1026 compatible = "qcom,apq8064-ahci", "generic-ahci";
1036 clock-names = "slave_iface",
1042 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
1044 assigned-clock-rates = <100000000>, <100000000>;
1047 phy-names = "sata-phy";
1048 ports-implemented = <0x1>;
1053 compatible = "qcom,bam-v1.3.0";
1057 clock-names = "bam_clk";
1058 #dma-cells = <1>;
1063 compatible = "qcom,bam-v1.3.0";
1067 clock-names = "bam_clk";
1068 #dma-cells = <1>;
1073 compatible = "qcom,bam-v1.3.0";
1077 clock-names = "bam_clk";
1078 #dma-cells = <1>;
1083 compatible = "simple-bus";
1084 #address-cells = <1>;
1085 #size-cells = <1>;
1090 pinctrl-names = "default";
1091 pinctrl-0 = <&sdcc1_pins>;
1092 arm,primecell-periphid = <0x00051180>;
1095 interrupt-names = "cmd_irq";
1097 clock-names = "mclk", "apb_pclk";
1098 bus-width = <8>;
1099 max-frequency = <96000000>;
1100 non-removable;
1101 cap-sd-highspeed;
1102 cap-mmc-highspeed;
1104 dma-names = "tx", "rx";
1109 arm,primecell-periphid = <0x00051180>;
1113 interrupt-names = "cmd_irq";
1115 clock-names = "mclk", "apb_pclk";
1116 bus-width = <4>;
1117 cap-sd-highspeed;
1118 cap-mmc-highspeed;
1119 max-frequency = <192000000>;
1120 no-1-8-v;
1122 dma-names = "tx", "rx";
1127 arm,primecell-periphid = <0x00051180>;
1131 interrupt-names = "cmd_irq";
1133 clock-names = "mclk", "apb_pclk";
1134 bus-width = <4>;
1135 cap-sd-highspeed;
1136 cap-mmc-highspeed;
1137 max-frequency = <48000000>;
1139 dma-names = "tx", "rx";
1140 pinctrl-names = "default";
1141 pinctrl-0 = <&sdc4_gpios>;
1146 compatible = "qcom,tcsr-apq8064", "syscon";
1150 gpu: adreno-3xx@4300000 {
1151 compatible = "qcom,adreno-3xx";
1153 reg-names = "kgsl_3d0_reg_memory";
1155 interrupt-names = "kgsl_3d0_irq";
1156 clock-names =
1233 qcom,gpu-pwrlevels {
1234 compatible = "qcom,gpu-pwrlevels";
1235 qcom,gpu-pwrlevel@0 {
1236 qcom,gpu-freq = <450000000>;
1238 qcom,gpu-pwrlevel@1 {
1239 qcom,gpu-freq = <27000000>;
1250 compatible = "qcom,mdss-dsi-ctrl";
1251 label = "MDSS DSI CTRL->0";
1252 #address-cells = <1>;
1253 #size-cells = <0>;
1256 reg-names = "dsi_ctrl";
1265 clock-names = "iface_clk", "bus_clk", "core_mmss_clk",
1269 assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
1273 assigned-clock-parents = <&dsi0_phy 0>,
1277 syscon-sfpb = <&mmss_sfpb>;
1280 #address-cells = <1>;
1281 #size-cells = <0>;
1298 dsi0_phy: dsi-phy@4700200 {
1299 compatible = "qcom,dsi-phy-28nm-8960";
1300 #clock-cells = <1>;
1301 #phy-cells = <0>;
1306 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
1307 clock-names = "iface_clk", "ref";
1314 compatible = "qcom,apq8064-iommu";
1315 #iommu-cells = <1>;
1316 clock-names =
1330 compatible = "qcom,apq8064-iommu";
1331 #iommu-cells = <1>;
1332 clock-names =
1346 compatible = "qcom,apq8064-iommu";
1347 #iommu-cells = <1>;
1348 clock-names =
1362 compatible = "qcom,apq8064-iommu";
1363 #iommu-cells = <1>;
1364 clock-names =
1378 compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
1383 reg-names = "dbi", "elbi", "parf", "config";
1385 linux,pci-domain = <0>;
1386 bus-range = <0x00 0xff>;
1387 num-lanes = <1>;
1388 #address-cells = <3>;
1389 #size-cells = <2>;
1393 interrupt-names = "msi";
1394 #interrupt-cells = <1>;
1395 interrupt-map-mask = <0 0 0 0x7>;
1396 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1403 clock-names = "core", "iface", "phy";
1409 reset-names = "axi", "ahb", "por", "pci", "phy";
1413 hdmi: hdmi-tx@4a00000 {
1414 compatible = "qcom,hdmi-tx-8960";
1415 pinctrl-names = "default";
1416 pinctrl-0 = <&hdmi_pinctrl>;
1418 reg-names = "core_physical";
1423 clock-names = "core_clk",
1428 phy-names = "hdmi-phy";
1431 #address-cells = <1>;
1432 #size-cells = <0>;
1448 hdmi_phy: hdmi-phy@4a00400 {
1449 compatible = "qcom,hdmi-phy-8960";
1452 reg-names = "hdmi_phy",
1456 clock-names = "slave_iface_clk";
1457 #phy-cells = <0>;
1470 clock-names = "core_clk",
1483 #address-cells = <1>;
1484 #size-cells = <0>;
1512 riva: riva-pil@3204000 {
1513 compatible = "qcom,riva-pil";
1516 reg-names = "ccu", "dxe", "pmu";
1518 interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
1520 interrupt-names = "wdog", "fatal";
1522 memory-region = <&wcnss_mem>;
1524 vddcx-supply = <&pm8921_s3>;
1525 vddmx-supply = <&pm8921_l24>;
1526 vddpx-supply = <&pm8921_s4>;
1534 clock-names = "xo";
1536 vddxo-supply = <&pm8921_l4>;
1537 vddrfa-supply = <&pm8921_s2>;
1538 vddpa-supply = <&pm8921_l10>;
1539 vdddig-supply = <&pm8921_lvs2>;
1542 smd-edge {
1546 qcom,smd-edge = <6>;
1552 qcom,smd-channels = "WCNSS_CTRL";
1557 compatible = "qcom,wcnss-bt";
1561 compatible = "qcom,wcnss-wlan";
1565 interrupt-names = "tx", "rx";
1567 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1568 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1575 compatible = "coresight-etb10", "arm,primecell";
1579 clock-names = "apb_pclk";
1581 in-ports {
1584 remote-endpoint = <&replicator_out0>;
1591 compatible = "arm,coresight-tpiu", "arm,primecell";
1595 clock-names = "apb_pclk";
1597 in-ports {
1600 remote-endpoint = <&replicator_out1>;
1607 compatible = "arm,coresight-static-replicator";
1610 clock-names = "apb_pclk";
1612 out-ports {
1613 #address-cells = <1>;
1614 #size-cells = <0>;
1619 remote-endpoint = <&etb_in>;
1625 remote-endpoint = <&tpiu_in>;
1630 in-ports {
1633 remote-endpoint = <&funnel_out>;
1640 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1644 clock-names = "apb_pclk";
1646 in-ports {
1647 #address-cells = <1>;
1648 #size-cells = <0>;
1652 * 2 - connected to STM component
1653 * 3 - not-connected
1654 * 6 - not-connected
1655 * 7 - not-connected
1660 remote-endpoint = <&etm0_out>;
1666 remote-endpoint = <&etm1_out>;
1672 remote-endpoint = <&etm2_out>;
1678 remote-endpoint = <&etm3_out>;
1683 out-ports {
1686 remote-endpoint = <&replicator_in>;
1693 compatible = "arm,coresight-etm3x", "arm,primecell";
1697 clock-names = "apb_pclk";
1701 out-ports {
1704 remote-endpoint = <&funnel_in0>;
1711 compatible = "arm,coresight-etm3x", "arm,primecell";
1715 clock-names = "apb_pclk";
1719 out-ports {
1722 remote-endpoint = <&funnel_in1>;
1729 compatible = "arm,coresight-etm3x", "arm,primecell";
1733 clock-names = "apb_pclk";
1737 out-ports {
1740 remote-endpoint = <&funnel_in4>;
1747 compatible = "arm,coresight-etm3x", "arm,primecell";
1751 clock-names = "apb_pclk";
1755 out-ports {
1758 remote-endpoint = <&funnel_in5>;
1765 #include "qcom-apq8064-pins.dtsi"