Lines Matching +full:mmu +full:- +full:500
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/omap.h>
12 #include <dt-bindings/clock/omap5.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 interrupt-parent = <&wakeupgen>;
39 #address-cells = <1>;
40 #size-cells = <0>;
44 compatible = "arm,cortex-a15";
47 operating-points = <
54 clock-names = "cpu";
56 clock-latency = <300000>; /* From omap-cpufreq driver */
59 #cooling-cells = <2>; /* min followed by max */
63 compatible = "arm,cortex-a15";
66 operating-points = <
73 clock-names = "cpu";
75 clock-latency = <300000>; /* From omap-cpufreq driver */
78 #cooling-cells = <2>; /* min followed by max */
82 thermal-zones {
83 #include "omap4-cpu-thermal.dtsi"
84 #include "omap5-gpu-thermal.dtsi"
85 #include "omap5-core-thermal.dtsi"
89 compatible = "arm,armv7-timer";
95 interrupt-parent = <&gic>;
99 compatible = "arm,cortex-a15-pmu";
104 gic: interrupt-controller@48211000 {
105 compatible = "arm,cortex-a15-gic";
106 interrupt-controller;
107 #interrupt-cells = <3>;
112 interrupt-parent = <&gic>;
115 wakeupgen: interrupt-controller@48281000 {
116 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
117 interrupt-controller;
118 #interrupt-cells = <3>;
120 interrupt-parent = <&gic>;
128 compatible = "ti,omap-infra";
130 compatible = "ti,omap4-mpu";
144 compatible = "ti,omap5-l3-noc", "simple-bus";
145 #address-cells = <1>;
146 #size-cells = <1>;
148 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
169 compatible = "mmio-sram";
174 compatible = "ti,omap4430-gpmc";
176 #address-cells = <2>;
177 #size-cells = <1>;
180 dma-names = "rxtx";
181 gpmc,num-cs = <8>;
182 gpmc,num-waitpins = <4>;
185 clock-names = "fck";
186 interrupt-controller;
187 #interrupt-cells = <2>;
188 gpio-controller;
189 #gpio-cells = <2>;
192 target-module@55082000 {
193 compatible = "ti,sysc-omap2", "ti,sysc";
197 reg-names = "rev", "sysc", "syss";
198 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
201 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
205 clock-names = "fck";
207 reset-names = "rstctrl";
209 #size-cells = <1>;
210 #address-cells = <1>;
212 mmu_ipu: mmu@0 {
213 compatible = "ti,omap4-iommu";
216 #iommu-cells = <0>;
217 ti,iommu-bus-err-back;
222 compatible = "ti,omap5-dsp";
227 firmware-name = "omap5-dsp-fw.xe64T";
233 compatible = "ti,omap5-ipu";
235 reg-names = "l2ram";
239 firmware-name = "omap5-ipu-fw.xem4";
245 compatible = "ti,omap5-dmm";
252 compatible = "ti,emif-4d5";
254 ti,no-idle-on-init;
255 phy-type = <2>; /* DDR PHY type: Intelli PHY */
258 hw-caps-read-idle-ctrl;
259 hw-caps-ll-interface;
260 hw-caps-temp-alert;
264 compatible = "ti,emif-4d5";
266 ti,no-idle-on-init;
267 phy-type = <2>; /* DDR PHY type: Intelli PHY */
270 hw-caps-read-idle-ctrl;
271 hw-caps-ll-interface;
272 hw-caps-temp-alert;
275 aes1_target: target-module@4b501000 {
276 compatible = "ti,sysc-omap2", "ti,sysc";
280 reg-names = "rev", "sysc", "syss";
281 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
283 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
287 ti,syss-mask = <1>;
290 clock-names = "fck";
291 #address-cells = <1>;
292 #size-cells = <1>;
296 compatible = "ti,omap4-aes";
300 dma-names = "tx", "rx";
304 aes2_target: target-module@4b701000 {
305 compatible = "ti,sysc-omap2", "ti,sysc";
309 reg-names = "rev", "sysc", "syss";
310 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
312 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
316 ti,syss-mask = <1>;
319 clock-names = "fck";
320 #address-cells = <1>;
321 #size-cells = <1>;
325 compatible = "ti,omap4-aes";
329 dma-names = "tx", "rx";
333 sham_target: target-module@4b100000 {
334 compatible = "ti,sysc-omap3-sham", "ti,sysc";
338 reg-names = "rev", "sysc", "syss";
339 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
341 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
344 ti,syss-mask = <1>;
347 clock-names = "fck";
348 #address-cells = <1>;
349 #size-cells = <1>;
353 compatible = "ti,omap4-sham";
357 dma-names = "rx";
367 compatible = "ti,omap5430-bandgap";
369 #thermal-sensor-cells = <1>;
374 compatible = "snps,dwc-ahci";
378 phy-names = "sata-phy";
381 ports-implemented = <0x1>;
384 target-module@56000000 {
385 compatible = "ti,sysc-omap4", "ti,sysc";
388 reg-names = "rev", "sysc";
389 ti,sysc-midle = <SYSC_IDLE_FORCE>,
392 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
396 clock-names = "fck";
397 #address-cells = <1>;
398 #size-cells = <1>;
407 target-module@58000000 {
408 compatible = "ti,sysc-omap2", "ti,sysc";
411 reg-names = "rev", "syss";
412 ti,syss-mask = <1>;
417 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
418 #address-cells = <1>;
419 #size-cells = <1>;
423 compatible = "ti,omap5-dss";
427 clock-names = "fck";
428 #address-cells = <1>;
429 #size-cells = <1>;
432 target-module@1000 {
433 compatible = "ti,sysc-omap2", "ti,sysc";
437 reg-names = "rev", "sysc", "syss";
438 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
441 ti,sysc-midle = <SYSC_IDLE_FORCE>,
444 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
448 ti,syss-mask = <1>;
450 clock-names = "fck";
451 #address-cells = <1>;
452 #size-cells = <1>;
456 compatible = "ti,omap5-dispc";
460 clock-names = "fck";
464 target-module@2000 {
465 compatible = "ti,sysc-omap2", "ti,sysc";
469 reg-names = "rev", "sysc", "syss";
470 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
473 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
475 ti,syss-mask = <1>;
477 clock-names = "fck";
478 #address-cells = <1>;
479 #size-cells = <1>;
483 compatible = "ti,omap5-rfbi";
487 clock-names = "fck", "ick";
491 target-module@4000 {
492 compatible = "ti,sysc-omap2", "ti,sysc";
496 reg-names = "rev", "sysc", "syss";
497 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
500 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
504 ti,syss-mask = <1>;
505 #address-cells = <1>;
506 #size-cells = <1>;
510 compatible = "ti,omap5-dsi";
514 reg-names = "proto", "phy", "pll";
519 clock-names = "fck", "sys_clk";
523 target-module@9000 {
524 compatible = "ti,sysc-omap2", "ti,sysc";
528 reg-names = "rev", "sysc", "syss";
529 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
532 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
536 ti,syss-mask = <1>;
537 #address-cells = <1>;
538 #size-cells = <1>;
542 compatible = "ti,omap5-dsi";
546 reg-names = "proto", "phy", "pll";
551 clock-names = "fck", "sys_clk";
555 target-module@40000 {
556 compatible = "ti,sysc-omap4", "ti,sysc";
559 reg-names = "rev", "sysc";
560 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
564 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
567 clock-names = "fck", "dss_clk";
568 #address-cells = <1>;
569 #size-cells = <1>;
573 compatible = "ti,omap5-hdmi";
578 reg-names = "wp", "pll", "phy", "core";
583 clock-names = "fck", "sys_clk";
585 dma-names = "audio_tx";
591 abb_mpu: regulator-abb-mpu {
592 compatible = "ti,abb-v2";
593 regulator-name = "abb_mpu";
594 #address-cells = <0>;
595 #size-cells = <0>;
597 ti,settling-time = <50>;
598 ti,clock-cycles = <16>;
602 reg-names = "base-address", "int-address",
603 "efuse-address", "ldo-address";
604 ti,tranxdone-status-mask = <0x80>;
606 ti,ldovbb-override-mask = <0x400>;
608 ti,ldovbb-vset-mask = <0x1F>;
621 abb_mm: regulator-abb-mm {
622 compatible = "ti,abb-v2";
623 regulator-name = "abb_mm";
624 #address-cells = <0>;
625 #size-cells = <0>;
627 ti,settling-time = <50>;
628 ti,clock-cycles = <16>;
632 reg-names = "base-address", "int-address",
633 "efuse-address", "ldo-address";
634 ti,tranxdone-status-mask = <0x80000000>;
636 ti,ldovbb-override-mask = <0x400>;
638 ti,ldovbb-vset-mask = <0x1F>;
654 polling-delay = <500>; /* milliseconds */
655 coefficients = <65 (-1791)>;
658 #include "omap5-l4.dtsi"
659 #include "omap54xx-clocks.dtsi"
662 coefficients = <117 (-2992)>;
669 #include "omap5-l4-abe.dtsi"
670 #include "omap54xx-clocks.dtsi"
674 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
676 #reset-cells = <1>;
679 prm_abe: prm@500 {
680 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
682 #power-domain-cells = <0>;
686 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
688 #reset-cells = <1>;
692 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
694 #reset-cells = <1>;
698 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
700 #reset-cells = <1>;
704 /* Preferred always-on timer for clockevent */
706 ti,no-reset-on-init;
707 ti,no-idle;
709 assigned-clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
710 assigned-clock-parents = <&sys_32k_ck>;