Lines Matching +full:0 +full:x4c000000
40 #size-cells = <0>;
42 cpu0: cpu@0 {
45 reg = <0x0>;
64 reg = <0x1>;
108 reg = <0 0x48211000 0 0x1000>,
109 <0 0x48212000 0 0x2000>,
110 <0 0x48214000 0 0x2000>,
111 <0 0x48216000 0 0x2000>;
119 reg = <0 0x48281000 0 0x1000>;
147 ranges = <0 0 0 0xc0000000>;
148 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
150 reg = <0 0x44000000 0 0x2000>,
151 <0 0x44800000 0 0x3000>,
152 <0 0x45000000 0 0x4000>;
170 reg = <0x40300000 0x20000>; /* 128k */
175 reg = <0x50000000 0x1000>;
194 reg = <0x55082000 0x4>,
195 <0x55082010 0x4>,
196 <0x55082014 0x4>;
204 clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
208 ranges = <0x0 0x55082000 0x100>;
212 mmu_ipu: mmu@0 {
214 reg = <0x0 0x100>;
216 #iommu-cells = <0>;
223 ti,bootreg = <&scm_conf 0x304 0>;
225 resets = <&prm_dsp 0>;
226 clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>;
234 reg = <0x55020000 0x10000>;
237 resets = <&prm_core 0>, <&prm_core 1>;
238 clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
246 reg = <0x4e000000 0x800>;
247 interrupts = <0 113 0x4>;
256 reg = <0x4c000000 0x400>;
268 reg = <0x4d000000 0x400>;
277 reg = <0x4b501080 0x4>,
278 <0x4b501084 0x4>,
279 <0x4b501088 0x4>;
289 clocks = <&l4sec_clkctrl OMAP5_AES1_CLKCTRL 0>;
293 ranges = <0x0 0x4b501000 0x1000>;
295 aes1: aes@0 {
297 reg = <0 0xa0>;
306 reg = <0x4b701080 0x4>,
307 <0x4b701084 0x4>,
308 <0x4b701088 0x4>;
318 clocks = <&l4sec_clkctrl OMAP5_AES2_CLKCTRL 0>;
322 ranges = <0x0 0x4b701000 0x1000>;
324 aes2: aes@0 {
326 reg = <0 0xa0>;
335 reg = <0x4b100100 0x4>,
336 <0x4b100110 0x4>,
337 <0x4b100114 0x4>;
346 clocks = <&l4sec_clkctrl OMAP5_SHA2MD5_CLKCTRL 0>;
350 ranges = <0x0 0x4b100000 0x1000>;
352 sham: sham@0 {
354 reg = <0 0x300>;
362 reg = <0x4a0021e0 0xc
363 0x4a00232c 0xc
364 0x4a002380 0x2c
365 0x4a0023C0 0x3c>;
375 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
381 ports-implemented = <0x1>;
386 reg = <0x5600fe00 0x4>,
387 <0x5600fe10 0x4>;
395 clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>;
399 ranges = <0 0x56000000 0x2000000>;
409 reg = <0x58000000 4>,
410 <0x58000014 4>;
413 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>,
420 ranges = <0 0x58000000 0x1000000>;
422 dss: dss@0 {
424 reg = <0 0x80>;
430 ranges = <0 0 0x1000000>;
434 reg = <0x1000 0x4>,
435 <0x1010 0x4>,
436 <0x1014 0x4>;
453 ranges = <0 0x1000 0x1000>;
455 dispc@0 {
457 reg = <0 0x1000>;
466 reg = <0x2000 0x4>,
467 <0x2010 0x4>,
468 <0x2014 0x4>;
480 ranges = <0 0x2000 0x1000>;
482 rfbi: encoder@0 {
484 reg = <0 0x100>;
493 reg = <0x4000 0x4>,
494 <0x4010 0x4>,
495 <0x4014 0x4>;
507 ranges = <0 0x4000 0x1000>;
509 dsi1: encoder@0 {
511 reg = <0 0x200>,
512 <0x200 0x40>,
513 <0x300 0x40>;
525 reg = <0x9000 0x4>,
526 <0x9010 0x4>,
527 <0x9014 0x4>;
539 ranges = <0 0x9000 0x1000>;
541 dsi2: encoder@0 {
543 reg = <0 0x200>,
544 <0x200 0x40>,
545 <0x300 0x40>;
557 reg = <0x40000 0x4>,
558 <0x40010 0x4>;
570 ranges = <0 0x40000 0x40000>;
572 hdmi: encoder@0 {
574 reg = <0 0x200>,
575 <0x200 0x80>,
576 <0x300 0x80>,
577 <0x20000 0x19000>;
594 #address-cells = <0>;
595 #size-cells = <0>;
600 reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
601 <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
604 ti,tranxdone-status-mask = <0x80>;
606 ti,ldovbb-override-mask = <0x400>;
608 ti,ldovbb-vset-mask = <0x1F>;
616 1060000 0 0x0 0 0x02000000 0x01F00000
617 1250000 0 0x4 0 0x02000000 0x01F00000
624 #address-cells = <0>;
625 #size-cells = <0>;
630 reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
631 <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
634 ti,tranxdone-status-mask = <0x80000000>;
636 ti,ldovbb-override-mask = <0x400>;
638 ti,ldovbb-vset-mask = <0x1F>;
646 1025000 0 0x0 0 0x02000000 0x01F00000
647 1120000 0 0x4 0 0x02000000 0x01F00000
666 coefficients = <0 2000>;
675 reg = <0x400 0x100>;
681 reg = <0x500 0x100>;
682 #power-domain-cells = <0>;
687 reg = <0x700 0x100>;
693 reg = <0x1200 0x100>;
699 reg = <0x1c00 0x100>;
708 timer@0 {