Lines Matching +full:0 +full:x4c000000
35 #size-cells = <0>;
37 cpu@0 {
41 reg = <0x0>;
52 reg = <0x1>;
71 reg = <0x48241000 0x1000>,
72 <0x48240100 0x0100>;
78 reg = <0x48242000 0x1000>;
86 reg = <0x48240600 0x20>;
95 reg = <0x48281000 0x1000>;
130 reg = <0x44000000 0x1000>,
131 <0x44800000 0x2000>,
132 <0x45000000 0x1000>;
150 reg = <0x40304000 0xa000>; /* 40k */
155 reg = <0x50000000 0x1000>;
176 reg = <0x52000000 0x4>,
177 <0x52000010 0x4>;
189 clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;
193 ranges = <0 0x52000000 0x1000000>;
200 reg = <0x55082000 0x4>,
201 <0x55082010 0x4>,
202 <0x55082014 0x4>;
210 clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
214 ranges = <0x0 0x55082000 0x100>;
218 mmu_ipu: mmu@0 {
220 reg = <0x0 0x100>;
222 #iommu-cells = <0>;
229 reg = <0x4012c000 0x4>,
230 <0x4012c010 0x4>;
237 clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>;
241 ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */
242 <0x4902c000 0x4902c000 0x1000>; /* L3 */
249 reg = <0x4e000000 0x800>;
250 interrupts = <0 113 0x4>;
256 reg = <0x4c000000 0x100>;
268 reg = <0x4d000000 0x100>;
280 ti,bootreg = <&scm_conf 0x304 0>;
282 resets = <&prm_tesla 0>;
283 clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
291 reg = <0x55020000 0x10000>;
294 resets = <&prm_core 0>, <&prm_core 1>;
295 clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
303 reg = <0x4b501080 0x4>,
304 <0x4b501084 0x4>,
305 <0x4b501088 0x4>;
315 clocks = <&l4_secure_clkctrl OMAP4_AES1_CLKCTRL 0>;
319 ranges = <0x0 0x4b501000 0x1000>;
321 aes1: aes@0 {
323 reg = <0 0xa0>;
332 reg = <0x4b701080 0x4>,
333 <0x4b701084 0x4>,
334 <0x4b701088 0x4>;
344 clocks = <&l4_secure_clkctrl OMAP4_AES2_CLKCTRL 0>;
348 ranges = <0x0 0x4b701000 0x1000>;
350 aes2: aes@0 {
352 reg = <0 0xa0>;
361 reg = <0x4b100100 0x4>,
362 <0x4b100110 0x4>,
363 <0x4b100114 0x4>;
372 clocks = <&l4_secure_clkctrl OMAP4_SHA2MD5_CLKCTRL 0>;
376 ranges = <0x0 0x4b100000 0x1000>;
378 sham: sham@0 {
380 reg = <0 0x300>;
390 #address-cells = <0>;
391 #size-cells = <0>;
392 ti,tranxdone-status-mask = <0x80>;
403 #address-cells = <0>;
404 #size-cells = <0>;
405 ti,tranxdone-status-mask = <0x80000000>;
415 reg = <0x5600fe00 0x4>,
416 <0x5600fe10 0x4>;
426 clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;
430 ranges = <0 0x56000000 0x2000000>;
444 reg = <0x58000000 4>,
445 <0x58000014 4>;
448 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>,
455 ranges = <0 0x58000000 0x1000000>;
457 dss: dss@0 {
459 reg = <0 0x80>;
465 ranges = <0 0 0x1000000>;
469 reg = <0x1000 0x4>,
470 <0x1010 0x4>,
471 <0x1014 0x4>;
489 ranges = <0 0x1000 0x1000>;
491 dispc@0 {
493 reg = <0 0x1000>;
502 reg = <0x2000 0x4>,
503 <0x2010 0x4>,
504 <0x2014 0x4>;
517 ranges = <0 0x2000 0x1000>;
519 rfbi: encoder@0 {
520 reg = <0 0x1000>;
529 reg = <0x3000 0x4>;
535 ranges = <0 0x3000 0x1000>;
537 venc: encoder@0 {
539 reg = <0 0x1000>;
548 reg = <0x4000 0x4>,
549 <0x4010 0x4>,
550 <0x4014 0x4>;
562 ranges = <0 0x4000 0x1000>;
564 dsi1: encoder@0 {
566 reg = <0 0x200>,
567 <0x200 0x40>,
568 <0x300 0x20>;
577 #size-cells = <0>;
583 reg = <0x5000 0x4>,
584 <0x5010 0x4>,
585 <0x5014 0x4>;
597 ranges = <0 0x5000 0x1000>;
599 dsi2: encoder@0 {
601 reg = <0 0x200>,
602 <0x200 0x40>,
603 <0x300 0x20>;
612 #size-cells = <0>;
618 reg = <0x6000 0x4>,
619 <0x6010 0x4>;
633 ranges = <0 0x6000 0x2000>;
635 hdmi: encoder@0 {
637 reg = <0 0x200>,
638 <0x200 0x100>,
639 <0x300 0x100>,
640 <0x400 0x1000>;
663 reg = <0x400 0x100>;
669 reg = <0x500 0x100>;
670 #power-domain-cells = <0>;
675 reg = <0x700 0x100>;
681 reg = <0xf00 0x100>;
687 reg = <0x1b00 0x40>;
696 timer@0 {