Lines Matching full:topckgen
98 clocks = <&topckgen CLK_TOP_HIF_SEL>;
100 assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
101 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
138 topckgen: syscon@10210000 { label
139 compatible = "mediatek,mt7629-topckgen", "syscon";
216 clocks = <&topckgen CLK_TOP_UART_SEL>,
227 clocks = <&topckgen CLK_TOP_UART_SEL>,
238 clocks = <&topckgen CLK_TOP_UART_SEL>,
248 clocks = <&topckgen CLK_TOP_PWM_SEL>,
252 assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
254 <&topckgen CLK_TOP_UNIVPLL2_D4>;
268 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
269 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
282 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
283 <&topckgen CLK_TOP_SPI0_SEL>,
294 <&topckgen CLK_TOP_FLASH_SEL>;
320 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
321 <&topckgen CLK_TOP_SATA_SEL>,
322 <&topckgen CLK_TOP_HIF_SEL>;
323 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
324 <&topckgen CLK_TOP_UNIVPLL2_D4>,
325 <&topckgen CLK_TOP_UNIVPLL1_D2>;
382 assigned-clocks = <&topckgen CLK_TOP_SATA_SEL>,
383 <&topckgen CLK_TOP_AXI_SEL>,
384 <&topckgen CLK_TOP_HIF_SEL>;
385 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL2_D4>,
386 <&topckgen CLK_TOP_SYSPLL1_D2>,
387 <&topckgen CLK_TOP_UNIVPLL1_D2>;
445 clocks = <&topckgen CLK_TOP_ETH_SEL>,
446 <&topckgen CLK_TOP_F10M_REF_SEL>,
468 assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
469 <&topckgen CLK_TOP_F10M_REF_SEL>;
470 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
471 <&topckgen CLK_TOP_SGMIIPLL_D2>;