Lines Matching full:topckgen
226 topckgen: syscon@10000000 { label
227 compatible = "mediatek,mt7623-topckgen",
228 "mediatek,mt2701-topckgen",
278 clocks = <&topckgen CLK_TOP_MM_SEL>,
279 <&topckgen CLK_TOP_MFG_SEL>,
280 <&topckgen CLK_TOP_ETHIF_SEL>;
424 clocks = <&topckgen CLK_TOP_PWM_SEL>,
488 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
489 <&topckgen CLK_TOP_SPI0_SEL>,
553 <&topckgen CLK_TOP_FLASH_SEL>;
567 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
568 <&topckgen CLK_TOP_SPI1_SEL>,
581 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
582 <&topckgen CLK_TOP_SPI2_SEL>,
604 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
605 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
606 <&topckgen CLK_TOP_AUD_48K_TIMING>,
607 <&topckgen CLK_TOP_AUD_44K_TIMING>,
608 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
609 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
610 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
611 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
612 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
613 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
614 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
615 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
616 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
617 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
618 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
619 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
673 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
674 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
675 <&topckgen CLK_TOP_AUD_MUX1_DIV>,
676 <&topckgen CLK_TOP_AUD_MUX2_DIV>;
677 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
678 <&topckgen CLK_TOP_AUD2PLL_90M>;
689 <&topckgen CLK_TOP_MSDC30_0_SEL>;
700 <&topckgen CLK_TOP_MSDC30_1_SEL>;
737 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
832 <&topckgen CLK_TOP_ETHIF_SEL>;
850 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
873 <&topckgen CLK_TOP_ETHIF_SEL>;
891 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
933 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,