Lines Matching +full:syscon +full:- +full:phy +full:- +full:power
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2017-2018 MediaTek Inc.
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/clock/mt2701-clk.h>
13 #include <dt-bindings/pinctrl/mt7623-pinfunc.h>
14 #include <dt-bindings/power/mt2701-power.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/phy/phy.h>
17 #include <dt-bindings/reset/mt2701-resets.h>
18 #include <dt-bindings/thermal/thermal.h>
22 interrupt-parent = <&sysirq>;
23 #address-cells = <2>;
24 #size-cells = <2>;
26 cpu_opp_table: opp-table {
27 compatible = "operating-points-v2";
28 opp-shared;
30 opp-98000000 {
31 opp-hz = /bits/ 64 <98000000>;
32 opp-microvolt = <1050000>;
35 opp-198000000 {
36 opp-hz = /bits/ 64 <198000000>;
37 opp-microvolt = <1050000>;
40 opp-398000000 {
41 opp-hz = /bits/ 64 <398000000>;
42 opp-microvolt = <1050000>;
45 opp-598000000 {
46 opp-hz = /bits/ 64 <598000000>;
47 opp-microvolt = <1050000>;
50 opp-747500000 {
51 opp-hz = /bits/ 64 <747500000>;
52 opp-microvolt = <1050000>;
55 opp-1040000000 {
56 opp-hz = /bits/ 64 <1040000000>;
57 opp-microvolt = <1150000>;
60 opp-1196000000 {
61 opp-hz = /bits/ 64 <1196000000>;
62 opp-microvolt = <1200000>;
65 opp-1300000000 {
66 opp-hz = /bits/ 64 <1300000000>;
67 opp-microvolt = <1300000>;
72 #address-cells = <1>;
73 #size-cells = <0>;
74 enable-method = "mediatek,mt6589-smp";
78 compatible = "arm,cortex-a7";
82 clock-names = "cpu", "intermediate";
83 operating-points-v2 = <&cpu_opp_table>;
84 #cooling-cells = <2>;
85 clock-frequency = <1300000000>;
90 compatible = "arm,cortex-a7";
94 clock-names = "cpu", "intermediate";
95 operating-points-v2 = <&cpu_opp_table>;
96 #cooling-cells = <2>;
97 clock-frequency = <1300000000>;
102 compatible = "arm,cortex-a7";
106 clock-names = "cpu", "intermediate";
107 operating-points-v2 = <&cpu_opp_table>;
108 #cooling-cells = <2>;
109 clock-frequency = <1300000000>;
114 compatible = "arm,cortex-a7";
118 clock-names = "cpu", "intermediate";
119 operating-points-v2 = <&cpu_opp_table>;
120 #cooling-cells = <2>;
121 clock-frequency = <1300000000>;
126 compatible = "arm,cortex-a7-pmu";
131 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
135 compatible = "fixed-clock";
136 clock-frequency = <13000000>;
137 #clock-cells = <0>;
140 rtc32k: oscillator-1 {
141 compatible = "fixed-clock";
142 #clock-cells = <0>;
143 clock-frequency = <32000>;
144 clock-output-names = "rtc32k";
147 clk26m: oscillator-0 {
148 compatible = "fixed-clock";
149 #clock-cells = <0>;
150 clock-frequency = <26000000>;
151 clock-output-names = "clk26m";
154 thermal-zones {
155 cpu_thermal: cpu-thermal {
156 polling-delay-passive = <1000>;
157 polling-delay = <1000>;
159 thermal-sensors = <&thermal 0>;
162 cpu_passive: cpu-passive {
168 cpu_active: cpu-active {
174 cpu_hot: cpu-hot {
180 cpu-crit {
187 cooling-maps {
190 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
198 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
206 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
216 compatible = "arm,armv7-timer";
217 interrupt-parent = <&gic>;
222 clock-frequency = <13000000>;
223 arm,cpu-registers-not-fw-configured;
226 topckgen: syscon@10000000 {
227 compatible = "mediatek,mt7623-topckgen",
228 "mediatek,mt2701-topckgen",
229 "syscon";
231 #clock-cells = <1>;
234 infracfg: syscon@10001000 {
235 compatible = "mediatek,mt7623-infracfg",
236 "mediatek,mt2701-infracfg",
237 "syscon";
239 #clock-cells = <1>;
240 #reset-cells = <1>;
243 pericfg: syscon@10003000 {
244 compatible = "mediatek,mt7623-pericfg",
245 "mediatek,mt2701-pericfg",
246 "syscon";
248 #clock-cells = <1>;
249 #reset-cells = <1>;
253 compatible = "mediatek,mt7623-pinctrl";
255 mediatek,pctl-regmap = <&syscfg_pctl_a>;
256 pins-are-numbered;
257 gpio-controller;
258 #gpio-cells = <2>;
259 interrupt-controller;
260 interrupt-parent = <&gic>;
261 #interrupt-cells = <2>;
267 compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
271 scpsys: power-controller@10006000 {
272 compatible = "mediatek,mt7623-scpsys",
273 "mediatek,mt2701-scpsys",
274 "syscon";
275 #power-domain-cells = <1>;
281 clock-names = "mm", "mfg", "ethif";
285 compatible = "mediatek,mt7623-wdt",
286 "mediatek,mt6589-wdt";
291 compatible = "mediatek,mt7623-timer",
292 "mediatek,mt6577-timer";
296 clock-names = "system-clk", "rtc-clk";
300 compatible = "mediatek,mt7623-pwrap",
301 "mediatek,mt2701-pwrap";
303 reg-names = "pwrap";
306 reset-names = "pwrap";
309 clock-names = "spi", "wrap";
313 compatible = "mediatek,mt7623-cir";
317 clock-names = "clk";
321 sysirq: interrupt-controller@10200100 {
322 compatible = "mediatek,mt7623-sysirq",
323 "mediatek,mt6577-sysirq";
324 interrupt-controller;
325 #interrupt-cells = <3>;
326 interrupt-parent = <&gic>;
331 compatible = "mediatek,mt7623-efuse",
332 "mediatek,mt8173-efuse";
334 #address-cells = <1>;
335 #size-cells = <1>;
341 apmixedsys: syscon@10209000 {
342 compatible = "mediatek,mt7623-apmixedsys",
343 "mediatek,mt2701-apmixedsys",
344 "syscon";
346 #clock-cells = <1>;
350 compatible = "mediatek,mt7623-rng";
353 clock-names = "rng";
356 gic: interrupt-controller@10211000 {
357 compatible = "arm,cortex-a7-gic";
358 interrupt-controller;
359 #interrupt-cells = <3>;
360 interrupt-parent = <&gic>;
368 compatible = "mediatek,mt7623-auxadc",
369 "mediatek,mt2701-auxadc";
372 clock-names = "main";
373 #io-channel-cells = <1>;
377 compatible = "mediatek,mt7623-uart",
378 "mediatek,mt6577-uart";
383 clock-names = "baud", "bus";
388 compatible = "mediatek,mt7623-uart",
389 "mediatek,mt6577-uart";
394 clock-names = "baud", "bus";
399 compatible = "mediatek,mt7623-uart",
400 "mediatek,mt6577-uart";
405 clock-names = "baud", "bus";
410 compatible = "mediatek,mt7623-uart",
411 "mediatek,mt6577-uart";
416 clock-names = "baud", "bus";
421 compatible = "mediatek,mt7623-pwm";
423 #pwm-cells = <2>;
431 clock-names = "top", "main", "pwm1", "pwm2",
437 compatible = "mediatek,mt7623-i2c",
438 "mediatek,mt6577-i2c";
442 clock-div = <16>;
445 clock-names = "main", "dma";
446 #address-cells = <1>;
447 #size-cells = <0>;
452 compatible = "mediatek,mt7623-i2c",
453 "mediatek,mt6577-i2c";
457 clock-div = <16>;
460 clock-names = "main", "dma";
461 #address-cells = <1>;
462 #size-cells = <0>;
467 compatible = "mediatek,mt7623-i2c",
468 "mediatek,mt6577-i2c";
472 clock-div = <16>;
475 clock-names = "main", "dma";
476 #address-cells = <1>;
477 #size-cells = <0>;
482 compatible = "mediatek,mt7623-spi",
483 "mediatek,mt2701-spi";
484 #address-cells = <1>;
485 #size-cells = <0>;
491 clock-names = "parent-clk", "sel-clk", "spi-clk";
496 #thermal-sensor-cells = <1>;
497 compatible = "mediatek,mt7623-thermal",
498 "mediatek,mt2701-thermal";
502 clock-names = "therm", "auxadc";
504 reset-names = "therm";
507 nvmem-cells = <&thermal_calibration_data>;
508 nvmem-cell-names = "calibration-data";
512 compatible = "mediatek,mt7623-btif",
513 "mediatek,mtk-btif";
517 clock-names = "main";
518 reg-shift = <2>;
519 reg-io-width = <4>;
524 compatible = "mediatek,mt7623-nfc",
525 "mediatek,mt2701-nfc";
528 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
531 clock-names = "nfi_clk", "pad_clk";
533 ecc-engine = <&bch>;
534 #address-cells = <1>;
535 #size-cells = <0>;
539 compatible = "mediatek,mt7623-ecc",
540 "mediatek,mt2701-ecc";
544 clock-names = "nfiecc_clk";
549 compatible = "mediatek,mt7623-nor",
550 "mediatek,mt8173-nor";
554 clock-names = "spi", "sf";
555 #address-cells = <1>;
556 #size-cells = <0>;
561 compatible = "mediatek,mt7623-spi",
562 "mediatek,mt2701-spi";
563 #address-cells = <1>;
564 #size-cells = <0>;
570 clock-names = "parent-clk", "sel-clk", "spi-clk";
575 compatible = "mediatek,mt7623-spi",
576 "mediatek,mt2701-spi";
577 #address-cells = <1>;
578 #size-cells = <0>;
584 clock-names = "parent-clk", "sel-clk", "spi-clk";
588 audsys: clock-controller@11220000 {
589 compatible = "mediatek,mt7623-audsys",
590 "mediatek,mt2701-audsys",
591 "syscon";
593 #clock-cells = <1>;
595 afe: audio-controller {
596 compatible = "mediatek,mt7623-audio",
597 "mediatek,mt2701-audio";
600 interrupt-names = "afe", "asys";
601 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
638 clock-names = "infra_sys_audio_clk",
673 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
677 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
679 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
684 compatible = "mediatek,mt7623-mmc",
685 "mediatek,mt2701-mmc";
690 clock-names = "source", "hclk";
695 compatible = "mediatek,mt7623-mmc",
696 "mediatek,mt2701-mmc";
701 clock-names = "source", "hclk";
705 vdecsys: syscon@16000000 {
706 compatible = "mediatek,mt7623-vdecsys",
707 "mediatek,mt2701-vdecsys",
708 "syscon";
710 #clock-cells = <1>;
713 hifsys: syscon@1a000000 {
714 compatible = "mediatek,mt7623-hifsys",
715 "mediatek,mt2701-hifsys",
716 "syscon";
718 #clock-cells = <1>;
719 #reset-cells = <1>;
723 compatible = "mediatek,mt7623-pcie";
729 reg-names = "subsys", "port0", "port1", "port2";
730 #address-cells = <3>;
731 #size-cells = <2>;
732 #interrupt-cells = <1>;
733 interrupt-map-mask = <0xf800 0 0 0>;
734 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
741 clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
745 reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
749 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
750 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
751 bus-range = <0x00 0xff>;
758 #address-cells = <3>;
759 #size-cells = <2>;
760 #interrupt-cells = <1>;
761 interrupt-map-mask = <0 0 0 0>;
762 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
769 #address-cells = <3>;
770 #size-cells = <2>;
771 #interrupt-cells = <1>;
772 interrupt-map-mask = <0 0 0 0>;
773 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
780 #address-cells = <3>;
781 #size-cells = <2>;
782 #interrupt-cells = <1>;
783 interrupt-map-mask = <0 0 0 0>;
784 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
790 pcie0_phy: pcie-phy@1a149000 {
791 compatible = "mediatek,generic-tphy-v1";
793 #address-cells = <2>;
794 #size-cells = <2>;
798 pcie0_port: pcie-phy@1a149900 {
801 clock-names = "ref";
802 #phy-cells = <1>;
807 pcie1_phy: pcie-phy@1a14a000 {
808 compatible = "mediatek,generic-tphy-v1";
810 #address-cells = <2>;
811 #size-cells = <2>;
815 pcie1_port: pcie-phy@1a14a900 {
818 clock-names = "ref";
819 #phy-cells = <1>;
825 compatible = "mediatek,mt7623-xhci",
826 "mediatek,mt8173-xhci";
829 reg-names = "mac", "ippc";
833 clock-names = "sys_ck", "ref_ck";
834 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
839 u3phy1: usb-phy@1a1c4000 {
840 compatible = "mediatek,mt7623-u3phy",
841 "mediatek,mt2701-u3phy";
843 #address-cells = <2>;
844 #size-cells = <2>;
848 u2port0: usb-phy@1a1c4800 {
851 clock-names = "ref";
852 #phy-cells = <1>;
856 u3port0: usb-phy@1a1c4900 {
859 clock-names = "ref";
860 #phy-cells = <1>;
866 compatible = "mediatek,mt7623-xhci",
867 "mediatek,mt8173-xhci";
870 reg-names = "mac", "ippc";
874 clock-names = "sys_ck", "ref_ck";
875 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
880 u3phy2: usb-phy@1a244000 {
881 compatible = "mediatek,mt7623-u3phy",
882 "mediatek,mt2701-u3phy";
884 #address-cells = <2>;
885 #size-cells = <2>;
889 u2port1: usb-phy@1a244800 {
892 clock-names = "ref";
893 #phy-cells = <1>;
897 u3port1: usb-phy@1a244900 {
900 clock-names = "ref";
901 #phy-cells = <1>;
906 ethsys: syscon@1b000000 {
907 compatible = "mediatek,mt7623-ethsys",
908 "mediatek,mt2701-ethsys",
909 "syscon";
911 #clock-cells = <1>;
912 #reset-cells = <1>;
915 hsdma: dma-controller@1b007000 {
916 compatible = "mediatek,mt7623-hsdma";
920 clock-names = "hsdma";
921 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
922 #dma-cells = <1>;
926 compatible = "mediatek,mt7623-eth",
927 "mediatek,mt2701-eth",
928 "syscon";
938 clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
942 reset-names = "fe", "gmac", "ppe";
943 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
946 #address-cells = <1>;
947 #size-cells = <0>;
952 compatible = "mediatek,eip97-crypto";
960 clock-names = "cryp";
961 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
965 bdpsys: syscon@1c000000 {
966 compatible = "mediatek,mt7623-bdpsys",
967 "mediatek,mt2701-bdpsys",
968 "syscon";
970 #clock-cells = <1>;
975 cir_pins_a:cir-default {
976 pins-cir {
978 bias-disable;
982 i2c0_pins_a: i2c0-default {
983 pins-i2c0 {
986 bias-disable;
990 i2c1_pins_a: i2c1-default {
991 pin-i2c1 {
994 bias-disable;
998 i2c1_pins_b: i2c1-alt {
999 pin-i2c1 {
1002 bias-disable;
1006 i2c2_pins_a: i2c2-default {
1007 pin-i2c2 {
1010 bias-disable;
1014 i2c2_pins_b: i2c2-alt {
1015 pin-i2c2 {
1018 bias-disable;
1022 i2s0_pins_a: i2s0-default {
1023 pin-i2s0 {
1029 drive-strength = <MTK_DRIVE_12mA>;
1030 bias-pull-down;
1034 i2s1_pins_a: i2s1-default {
1035 pin-i2s1 {
1041 drive-strength = <MTK_DRIVE_12mA>;
1042 bias-pull-down;
1046 key_pins_a: keys-alt {
1047 pins-keys {
1050 input-enable;
1054 led_pins_a: leds-alt {
1055 pins-leds {
1063 pins-cmd-dat {
1073 input-enable;
1074 bias-pull-up;
1077 pins-clk {
1079 bias-pull-down;
1082 pins-rst {
1084 bias-pull-up;
1089 pins-cmd-dat {
1099 input-enable;
1100 drive-strength = <MTK_DRIVE_2mA>;
1101 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
1104 pins-clk {
1106 drive-strength = <MTK_DRIVE_2mA>;
1107 bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
1110 pins-rst {
1112 bias-pull-up;
1117 pins-cmd-dat {
1123 input-enable;
1124 drive-strength = <MTK_DRIVE_4mA>;
1125 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1128 pins-clk {
1130 bias-pull-down;
1131 drive-strength = <MTK_DRIVE_4mA>;
1134 pins-wp {
1136 input-enable;
1137 bias-pull-up;
1140 pins-insert {
1142 bias-pull-up;
1147 pins-cmd-dat {
1153 input-enable;
1154 drive-strength = <MTK_DRIVE_4mA>;
1155 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1158 pins-clk {
1160 drive-strength = <MTK_DRIVE_4mA>;
1161 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1166 pins-ale {
1168 drive-strength = <MTK_DRIVE_8mA>;
1169 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1172 pins-dat {
1182 input-enable;
1183 drive-strength = <MTK_DRIVE_8mA>;
1184 bias-pull-up;
1187 pins-we {
1189 drive-strength = <MTK_DRIVE_8mA>;
1190 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1198 bias-disable;
1202 pwm_pins_a: pwm-default {
1203 pins-pwm {
1212 spi0_pins_a: spi0-default {
1213 pins-spi {
1218 bias-disable;
1222 spi1_pins_a: spi1-default {
1223 pins-spi {
1231 spi2_pins_a: spi2-default {
1232 pins-spi {
1240 uart0_pins_a: uart0-default {
1241 pins-dat {
1247 uart1_pins_a: uart1-default {
1248 pins-dat {
1254 uart2_pins_a: uart2-default {
1255 pins-dat {
1261 uart2_pins_b: uart2-alt {
1262 pins-dat {