Lines Matching +full:mmp +full:- +full:twsi
1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/marvell,mmp2.h>
8 #include <dt-bindings/power/marvell,mmp2.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
24 #address-cells = <1>;
25 #size-cells = <1>;
26 compatible = "simple-bus";
27 interrupt-parent = <&intc>;
30 L2: l2-cache {
31 compatible = "marvell,tauros2-cache";
32 marvell,tauros2-cache-features = <0x3>;
36 compatible = "mrvl,axi-bus", "simple-bus";
37 #address-cells = <1>;
38 #size-cells = <1>;
49 clock-names = "core", "bus";
50 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>;
53 intc: interrupt-controller@d4282000 {
54 compatible = "mrvl,mmp2-intc";
55 interrupt-controller;
56 #interrupt-cells = <1>;
58 mrvl,intc-nr-irqs = <64>;
61 intcmux4: interrupt-controller@d4282150 {
62 compatible = "mrvl,mmp2-mux-intc";
64 interrupt-controller;
65 #interrupt-cells = <1>;
67 reg-names = "mux status", "mux mask";
68 mrvl,intc-nr-irqs = <2>;
71 intcmux5: interrupt-controller@d4282154 {
72 compatible = "mrvl,mmp2-mux-intc";
74 interrupt-controller;
75 #interrupt-cells = <1>;
77 reg-names = "mux status", "mux mask";
78 mrvl,intc-nr-irqs = <2>;
79 mrvl,clr-mfp-irq = <1>;
82 intcmux9: interrupt-controller@d4282180 {
83 compatible = "mrvl,mmp2-mux-intc";
85 interrupt-controller;
86 #interrupt-cells = <1>;
88 reg-names = "mux status", "mux mask";
89 mrvl,intc-nr-irqs = <3>;
92 intcmux17: interrupt-controller@d4282158 {
93 compatible = "mrvl,mmp2-mux-intc";
95 interrupt-controller;
96 #interrupt-cells = <1>;
98 reg-names = "mux status", "mux mask";
99 mrvl,intc-nr-irqs = <5>;
102 intcmux35: interrupt-controller@d428215c {
103 compatible = "mrvl,mmp2-mux-intc";
105 interrupt-controller;
106 #interrupt-cells = <1>;
108 reg-names = "mux status", "mux mask";
109 mrvl,intc-nr-irqs = <15>;
112 intcmux51: interrupt-controller@d4282160 {
113 compatible = "mrvl,mmp2-mux-intc";
115 interrupt-controller;
116 #interrupt-cells = <1>;
118 reg-names = "mux status", "mux mask";
119 mrvl,intc-nr-irqs = <2>;
122 intcmux55: interrupt-controller@d4282188 {
123 compatible = "mrvl,mmp2-mux-intc";
125 interrupt-controller;
126 #interrupt-cells = <1>;
128 reg-names = "mux status", "mux mask";
129 mrvl,intc-nr-irqs = <2>;
132 usb_phy0: usb-phy@d4207000 {
133 compatible = "marvell,mmp2-usb-phy";
135 #phy-cells = <0>;
139 usb_otg0: usb-otg@d4208000 {
140 compatible = "marvell,pxau2o-ehci";
144 clock-names = "USBCLK";
146 phy-names = "usb";
151 compatible = "mrvl,pxav3-mmc";
154 clock-names = "io";
160 compatible = "mrvl,pxav3-mmc";
163 clock-names = "io";
169 compatible = "mrvl,pxav3-mmc";
172 clock-names = "io";
178 compatible = "mrvl,pxav3-mmc";
181 clock-names = "io";
187 compatible = "marvell,mmp2-ccic";
191 clock-names = "axi";
192 #clock-cells = <0>;
193 clock-output-names = "mclk";
198 compatible = "marvell,mmp2-ccic";
202 clock-names = "axi";
203 #clock-cells = <0>;
204 clock-output-names = "mclk";
208 adma0: dma-controller@d42a0800 {
209 compatible = "marvell,adma-1.0";
212 #dma-cells = <1>;
218 adma1: dma-controller@d42a0900 {
219 compatible = "marvell,adma-1.0";
222 #dma-cells = <1>;
227 compatible = "marvell,mmp2-audio-clock";
229 clock-names = "audio", "vctcxo", "i2s0", "i2s1";
234 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
235 #clock-cells = <1>;
239 sspa0: audio-controller@d42a0c00 {
240 compatible = "marvell,mmp-sspa";
244 clock-names = "audio", "bitclk";
247 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
248 #sound-dai-cells = <0>;
252 sspa1: audio-controller@d42a0d00 {
253 compatible = "marvell,mmp-sspa";
257 clock-names = "audio", "bitclk";
260 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
261 #sound-dai-cells = <0>;
267 compatible = "mrvl,apb-bus", "simple-bus";
268 #address-cells = <1>;
269 #size-cells = <1>;
273 dma-controller@d4000000 {
274 compatible = "marvell,pdma-1.0";
277 #dma-channels = <16>;
282 compatible = "mrvl,mmp-timer";
289 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
294 reg-shift = <2>;
299 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
304 reg-shift = <2>;
309 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
314 reg-shift = <2>;
319 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
324 reg-shift = <2>;
329 compatible = "marvell,mmp2-gpio";
330 #address-cells = <1>;
331 #size-cells = <1>;
333 gpio-controller;
334 #gpio-cells = <2>;
336 interrupt-names = "gpio_mux";
339 interrupt-controller;
340 #interrupt-cells = <2>;
369 compatible = "mrvl,mmp-twsi";
374 #address-cells = <1>;
375 #size-cells = <0>;
376 mrvl,i2c-fast-mode;
381 compatible = "mrvl,mmp-twsi";
383 interrupt-parent = <&intcmux17>;
387 #address-cells = <1>;
388 #size-cells = <0>;
393 compatible = "mrvl,mmp-twsi";
395 interrupt-parent = <&intcmux17>;
399 #address-cells = <1>;
400 #size-cells = <0>;
405 compatible = "mrvl,mmp-twsi";
407 interrupt-parent = <&intcmux17>;
411 #address-cells = <1>;
412 #size-cells = <0>;
418 compatible = "mrvl,mmp-twsi";
420 interrupt-parent = <&intcmux17>;
424 #address-cells = <1>;
425 #size-cells = <0>;
430 compatible = "mrvl,mmp-twsi";
432 interrupt-parent = <&intcmux17>;
436 #address-cells = <1>;
437 #size-cells = <0>;
442 compatible = "mrvl,mmp-rtc";
445 interrupt-names = "rtc 1Hz", "rtc alarm";
446 interrupt-parent = <&intcmux5>;
453 compatible = "marvell,mmp2-ssp";
457 #address-cells = <1>;
458 #size-cells = <0>;
463 compatible = "marvell,mmp2-ssp";
467 #address-cells = <1>;
468 #size-cells = <0>;
473 compatible = "marvell,mmp2-ssp";
477 #address-cells = <1>;
478 #size-cells = <0>;
483 compatible = "marvell,mmp2-ssp";
487 #address-cells = <1>;
488 #size-cells = <0>;
494 compatible = "mmio-sram";
497 #address-cells = <1>;
498 #size-cells = <1>;
503 compatible = "marvell,mmp2-clock";
507 reg-names = "mpmu", "apmu", "apbc";
508 #clock-cells = <1>;
509 #reset-cells = <1>;
510 #power-domain-cells = <1>;