Lines Matching +full:cortex +full:- +full:a8
1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 #include <dt-bindings/clock/meson8-ddr-clkc.h>
7 #include <dt-bindings/clock/meson8b-clkc.h>
8 #include <dt-bindings/gpio/meson8-gpio.h>
9 #include <dt-bindings/power/meson8-power.h>
10 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
19 #address-cells = <1>;
20 #size-cells = <0>;
24 compatible = "arm,cortex-a9";
25 next-level-cache = <&L2>;
27 enable-method = "amlogic,meson8-smp";
29 operating-points-v2 = <&cpu_opp_table>;
35 compatible = "arm,cortex-a9";
36 next-level-cache = <&L2>;
38 enable-method = "amlogic,meson8-smp";
40 operating-points-v2 = <&cpu_opp_table>;
46 compatible = "arm,cortex-a9";
47 next-level-cache = <&L2>;
49 enable-method = "amlogic,meson8-smp";
51 operating-points-v2 = <&cpu_opp_table>;
57 compatible = "arm,cortex-a9";
58 next-level-cache = <&L2>;
60 enable-method = "amlogic,meson8-smp";
62 operating-points-v2 = <&cpu_opp_table>;
67 cpu_opp_table: opp-table {
68 compatible = "operating-points-v2";
69 opp-shared;
71 opp-96000000 {
72 opp-hz = /bits/ 64 <96000000>;
73 opp-microvolt = <825000>;
75 opp-192000000 {
76 opp-hz = /bits/ 64 <192000000>;
77 opp-microvolt = <825000>;
79 opp-312000000 {
80 opp-hz = /bits/ 64 <312000000>;
81 opp-microvolt = <825000>;
83 opp-408000000 {
84 opp-hz = /bits/ 64 <408000000>;
85 opp-microvolt = <825000>;
87 opp-504000000 {
88 opp-hz = /bits/ 64 <504000000>;
89 opp-microvolt = <825000>;
91 opp-600000000 {
92 opp-hz = /bits/ 64 <600000000>;
93 opp-microvolt = <850000>;
95 opp-720000000 {
96 opp-hz = /bits/ 64 <720000000>;
97 opp-microvolt = <850000>;
99 opp-816000000 {
100 opp-hz = /bits/ 64 <816000000>;
101 opp-microvolt = <875000>;
103 opp-1008000000 {
104 opp-hz = /bits/ 64 <1008000000>;
105 opp-microvolt = <925000>;
107 opp-1200000000 {
108 opp-hz = /bits/ 64 <1200000000>;
109 opp-microvolt = <975000>;
111 opp-1416000000 {
112 opp-hz = /bits/ 64 <1416000000>;
113 opp-microvolt = <1025000>;
115 opp-1608000000 {
116 opp-hz = /bits/ 64 <1608000000>;
117 opp-microvolt = <1100000>;
119 opp-1800000000 {
121 opp-hz = /bits/ 64 <1800000000>;
122 opp-microvolt = <1125000>;
124 opp-1992000000 {
126 opp-hz = /bits/ 64 <1992000000>;
127 opp-microvolt = <1150000>;
131 gpu_opp_table: gpu-opp-table {
132 compatible = "operating-points-v2";
134 opp-182142857 {
135 opp-hz = /bits/ 64 <182142857>;
136 opp-microvolt = <1150000>;
138 opp-318750000 {
139 opp-hz = /bits/ 64 <318750000>;
140 opp-microvolt = <1150000>;
142 opp-425000000 {
143 opp-hz = /bits/ 64 <425000000>;
144 opp-microvolt = <1150000>;
146 opp-510000000 {
147 opp-hz = /bits/ 64 <510000000>;
148 opp-microvolt = <1150000>;
150 opp-637500000 {
151 opp-hz = /bits/ 64 <637500000>;
152 opp-microvolt = <1150000>;
153 turbo-mode;
158 compatible = "arm,cortex-a9-pmu";
163 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
166 reserved-memory {
167 #address-cells = <1>;
168 #size-cells = <1>;
174 no-map;
180 * piece of ARC code ("arc_power" in the vendor u-boot tree)
184 * simply the power key) and re-starts the ARM core once it
187 power-firmware@4f00000 {
189 no-map;
194 compatible = "simple-bus";
196 #address-cells = <1>;
197 #size-cells = <1>;
200 ddr_clkc: clock-controller@400 {
201 compatible = "amlogic,meson8-ddr-clkc";
204 clock-names = "xtal";
205 #clock-cells = <1>;
209 compatible = "simple-bus";
211 #address-cells = <1>;
212 #size-cells = <1>;
215 canvas: video-lut@20 {
216 compatible = "amlogic,meson8-canvas",
224 compatible = "simple-bus";
226 #address-cells = <1>;
227 #size-cells = <1>;
231 compatible = "amlogic,meson8-mali", "arm,mali-450";
249 interrupt-names = "gp", "gpmmu", "pp", "pmu",
255 clock-names = "bus", "core";
256 operating-points-v2 = <&gpu_opp_table>;
263 compatible = "amlogic,meson8-pmu", "syscon";
268 compatible = "amlogic,meson8-aobus-pinctrl";
270 #address-cells = <1>;
271 #size-cells = <1>;
274 gpio_ao: ao-bank@14 {
278 reg-names = "mux", "pull", "gpio";
279 gpio-controller;
280 #gpio-cells = <2>;
281 gpio-ranges = <&pinctrl_aobus 0 0 16>;
288 bias-disable;
296 bias-disable;
304 bias-disable;
308 pwm_f_ao_pins: pwm-f-ao {
312 bias-disable;
319 reset: reset-controller@4404 {
320 compatible = "amlogic,meson8b-reset";
322 #reset-cells = <1>;
325 analog_top: analog-top@81a8 {
326 compatible = "amlogic,meson8-analog-top", "syscon";
331 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
333 #pwm-cells = <3>;
337 clock-measure@8758 {
338 compatible = "amlogic,meson8-clk-measure";
343 compatible = "amlogic,meson8-cbus-pinctrl";
345 #address-cells = <1>;
346 #size-cells = <1>;
354 reg-names = "mux", "pull", "pull-enable", "gpio";
355 gpio-controller;
356 #gpio-cells = <2>;
357 gpio-ranges = <&pinctrl_cbus 0 0 120>;
360 sd_a_pins: sd-a {
365 bias-disable;
369 sd_b_pins: sd-b {
374 bias-disable;
378 sd_c_pins: sd-c {
383 bias-disable;
387 sdxc_b_pins: sdxc-b {
392 bias-pull-up;
400 bias-disable;
412 bias-disable;
416 pwm_e_pins: pwm-e {
420 bias-disable;
424 uart_a1_pins: uart-a1 {
429 bias-disable;
433 uart_a1_cts_rts_pins: uart-a1-cts-rts {
438 bias-disable;
445 smp-sram@1ff80 {
446 compatible = "amlogic,meson8-smp-sram";
452 compatible = "amlogic,meson8-efuse";
454 clock-names = "core";
464 clock-names = "stmmaceth";
466 power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>;
470 compatible = "amlogic,meson8-gpio-intc", "amlogic,meson-gpio-intc";
475 clkc: clock-controller {
476 compatible = "amlogic,meson8-clkc";
478 clock-names = "xtal", "ddr_pll";
479 #clock-cells = <1>;
480 #reset-cells = <1>;
483 pwrc: power-controller {
484 compatible = "amlogic,meson8-pwrc";
485 #power-domain-cells = <1>;
486 amlogic,ao-sysctrl = <&pmu>;
488 clock-names = "vpu";
489 assigned-clocks = <&clkc CLKID_VPU>;
490 assigned-clock-rates = <364285714>;
495 compatible = "amlogic,meson8-rng", "amlogic,meson-rng";
497 clock-names = "core";
513 arm,data-latency = <3 3 3>;
514 arm,tag-latency = <2 2 2>;
515 arm,filter-ranges = <0x100000 0xc0000000>;
516 prefetch-data = <1>;
517 prefetch-instr = <1>;
518 arm,shared-override;
523 compatible = "arm,cortex-a9-scu";
528 compatible = "arm,cortex-a9-global-timer";
541 compatible = "arm,cortex-a9-twd-timer";
549 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
553 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
557 compatible = "amlogic,meson8-rtc";
562 compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
564 clock-names = "clkin", "core";
565 amlogic,hhi-sysctrl = <&hhi>;
566 nvmem-cells = <&temperature_calib>;
567 nvmem-cell-names = "temperature_calib";
571 compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc";
577 clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk";
581 compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";
583 clock-names = "core", "clkin";
592 clock-names = "xtal", "pclk";
596 compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
598 clock-names = "baud", "xtal", "pclk";
602 compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
604 clock-names = "baud", "xtal", "pclk";
608 compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
610 clock-names = "baud", "xtal", "pclk";
614 compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
616 clock-names = "baud", "xtal", "pclk";
620 compatible = "amlogic,meson8-usb", "snps,dwc2";
622 clock-names = "otg";
626 compatible = "amlogic,meson8-usb", "snps,dwc2";
628 clock-names = "otg";
632 compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
634 clock-names = "usb_general", "usb";
639 compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
641 clock-names = "usb_general", "usb";