Lines Matching +full:arm926ej +full:- +full:s
1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2015-2019 Vladimir Zapolskiy <vz@mleia.com>
9 #include <dt-bindings/clock/lpc32xx-clock.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
16 interrupt-parent = <&mic>;
19 #address-cells = <1>;
20 #size-cells = <0>;
23 compatible = "arm,arm926ej-s";
31 compatible = "fixed-clock";
32 #clock-cells = <0>;
33 clock-frequency = <32768>;
34 clock-output-names = "xtal_32k";
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 clock-frequency = <13000000>;
41 clock-output-names = "xtal";
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "simple-bus";
54 compatible = "mmio-sram";
57 #address-cells = <1>;
58 #size-cells = <1>;
66 compatible = "nxp,lpc3220-slc";
73 compatible = "nxp,lpc3220-mlc";
85 clock-names = "apb_pclk";
89 #address-cells = <1>;
90 #size-cells = <1>;
91 compatible = "simple-bus";
98 compatible = "nxp,ohci-nxp", "usb-ohci";
100 interrupt-parent = <&sic1>;
107 compatible = "nxp,lpc3220-udc";
109 interrupt-parent = <&sic1>;
119 compatible = "nxp,pnx-i2c";
121 interrupt-parent = <&sic1>;
124 #address-cells = <1>;
125 #size-cells = <0>;
129 usbclk: clock-controller@f00 {
130 compatible = "nxp,lpc3220-usb-clk";
132 #clock-cells = <1>;
141 clock-names = "clcdclk", "apb_pclk";
146 compatible = "nxp,lpc-eth";
153 emc: memory-controller@31080000 {
157 clock-names = "mpmcclk", "apb_pclk";
158 #address-cells = <1>;
159 #size-cells = <1>;
169 #address-cells = <1>;
170 #size-cells = <1>;
171 compatible = "simple-bus";
183 clock-names = "apb_pclk";
184 #address-cells = <1>;
185 #size-cells = <0>;
190 compatible = "nxp,lpc3220-spi";
193 #address-cells = <1>;
194 #size-cells = <0>;
207 clock-names = "apb_pclk";
208 #address-cells = <1>;
209 #size-cells = <0>;
214 compatible = "nxp,lpc3220-spi";
217 #address-cells = <1>;
218 #size-cells = <0>;
223 compatible = "nxp,lpc3220-i2s";
234 clock-names = "apb_pclk";
239 compatible = "nxp,lpc3220-i2s";
247 compatible = "nxp,lpc3220-uart";
250 reg-shift = <2>;
256 compatible = "nxp,lpc3220-uart";
259 reg-shift = <2>;
265 compatible = "nxp,lpc3220-uart";
268 reg-shift = <2>;
274 compatible = "nxp,lpc3220-uart";
277 reg-shift = <2>;
283 compatible = "nxp,pnx-i2c";
285 interrupt-parent = <&sic1>;
287 #address-cells = <1>;
288 #size-cells = <0>;
294 compatible = "nxp,pnx-i2c";
296 interrupt-parent = <&sic1>;
298 #address-cells = <1>;
299 #size-cells = <0>;
305 compatible = "nxp,lpc3220-motor-pwm";
308 #pwm-cells = <2>;
313 #address-cells = <1>;
314 #size-cells = <1>;
315 compatible = "simple-bus";
320 compatible = "simple-bus";
322 #address-cells = <1>;
323 #size-cells = <1>;
325 clk: clock-controller@0 {
326 compatible = "nxp,lpc3220-clk";
328 #clock-cells = <1>;
331 clock-names = "xtal_32k", "xtal";
333 assigned-clocks = <&clk LPC32XX_CLK_HCLK_PLL>;
334 assigned-clock-rates = <208000000>;
338 mic: interrupt-controller@40008000 {
339 compatible = "nxp,lpc3220-mic";
341 interrupt-controller;
342 #interrupt-cells = <2>;
345 sic1: interrupt-controller@4000c000 {
346 compatible = "nxp,lpc3220-sic";
348 interrupt-controller;
349 #interrupt-cells = <2>;
351 interrupt-parent = <&mic>;
356 sic2: interrupt-controller@40010000 {
357 compatible = "nxp,lpc3220-sic";
359 interrupt-controller;
360 #interrupt-cells = <2>;
362 interrupt-parent = <&mic>;
368 compatible = "nxp,lpc3220-hsuart";
375 compatible = "nxp,lpc3220-hsuart";
382 compatible = "nxp,lpc3220-hsuart";
389 compatible = "nxp,lpc3220-rtc";
391 interrupt-parent = <&sic1>;
397 compatible = "nxp,lpc3220-gpio";
399 gpio-controller;
400 #gpio-cells = <3>; /* bank, pin, flags */
404 compatible = "nxp,lpc3220-timer";
408 clock-names = "timerclk";
413 compatible = "nxp,lpc3220-timer";
417 clock-names = "timerclk";
422 compatible = "nxp,pnx4008-wdt";
428 compatible = "nxp,lpc3220-timer";
431 clock-names = "timerclk";
443 compatible = "nxp,lpc3220-adc";
445 interrupt-parent = <&sic1>;
452 compatible = "nxp,lpc3220-tsc";
454 interrupt-parent = <&sic1>;
461 compatible = "nxp,lpc3220-timer";
465 clock-names = "timerclk";
469 compatible = "nxp,lpc3220-key";
472 interrupt-parent = <&sic1>;
478 compatible = "nxp,lpc3220-timer";
482 clock-names = "timerclk";
487 compatible = "nxp,lpc3220-pwm";
490 assigned-clocks = <&clk LPC32XX_CLK_PWM1>;
491 assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;
496 compatible = "nxp,lpc3220-pwm";
499 assigned-clocks = <&clk LPC32XX_CLK_PWM2>;
500 assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;
505 compatible = "nxp,lpc3220-timer";
509 clock-names = "timerclk";