Lines Matching +full:versatile +full:- +full:sysreg
1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
11 compatible = "arm,integrator-cp";
18 #address-cells = <1>;
19 #size-cells = <0>;
35 operating-points = <50000 0
38 clock-names = "cpu";
39 clock-latency = <1000000>; /* 1 ms */
45 * ARM DUI 0184B page 7-28 "Integrator/CP922T system clocks" which
51 #clock-cells = <0>;
52 compatible = "fixed-clock";
53 clock-frequency = <24576000>;
58 #clock-cells = <0>;
59 compatible = "fixed-factor-clock";
60 clock-div = <2>;
61 clock-mult = <1>;
67 #clock-cells = <0>;
68 compatible = "fixed-clock";
69 clock-frequency = <25000000>;
74 #clock-cells = <0>;
75 compatible = "fixed-clock";
76 clock-frequency = <14745600>;
81 #clock-cells = <0>;
82 compatible = "fixed-clock";
83 clock-frequency = <0>;
86 core-module@10000000 {
89 #clock-cells = <0>;
90 compatible = "fixed-clock";
91 clock-frequency = <24000000>;
96 compatible = "arm,syscon-icst525-integratorcp-cm-core";
97 #clock-cells = <0>;
98 lock-offset = <0x14>;
99 vco-offset = <0x08>;
105 compatible = "arm,syscon-icst525-integratorcp-cm-mem";
106 #clock-cells = <0>;
107 lock-offset = <0x14>;
108 vco-offset = <0x08>;
114 compatible = "arm,syscon-icst525";
115 #clock-cells = <0>;
116 lock-offset = <0x14>;
117 vco-offset = <0x1c>;
123 #clock-cells = <0>;
124 compatible = "fixed-factor-clock";
125 clock-div = <3>;
126 clock-mult = <1>;
132 #clock-cells = <0>;
133 compatible = "fixed-factor-clock";
134 clock-div = <24>;
135 clock-mult = <1>;
141 compatible = "arm,integrator-cp-syscon", "syscon";
147 compatible = "arm,integrator-cp-timer";
153 compatible = "arm,integrator-cp-timer";
159 compatible = "arm,integrator-cp-timer";
164 valid-mask = <0x1fc003ff>;
168 compatible = "arm,versatile-fpga-irq";
169 #interrupt-cells = <1>;
170 interrupt-controller;
172 clear-mask = <0xffffffff>;
173 valid-mask = <0x00000007>;
178 compatible = "arm,versatile-fpga-irq";
179 interrupt-parent = <&pic>;
181 #interrupt-cells = <1>;
182 interrupt-controller;
184 clear-mask = <0x00000fff>;
185 valid-mask = <0x00000fff>;
191 interrupt-parent = <&pic>;
197 #address-cells = <1>;
198 #size-cells = <0>;
201 #address-cells = <1>;
202 #size-cells = <0>;
208 remote-endpoint = <&clcd_pads_vga_dac>;
216 remote-endpoint = <&vga_con_in>;
223 compatible = "vga-connector";
227 remote-endpoint = <&vga_bridge_out>;
241 clock-names = "apb_pclk";
247 clock-names = "uartclk", "apb_pclk";
253 clock-names = "uartclk", "apb_pclk";
259 clock-names = "KMIREFCLK", "apb_pclk";
265 clock-names = "KMIREFCLK", "apb_pclk";
275 max-frequency = <515633>;
277 clock-names = "mclk", "apb_pclk";
285 clock-names = "apb_pclk";
293 clock-names = "clcdclk", "apb_pclk";
295 max-memory-bandwidth = <40000000>;
306 * FPGA "sysreg".
309 * ARM DUI 0225D, page 3-41, figure 3-19.
313 remote-endpoint = <&vga_bridge_in>;
314 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;