Lines Matching +full:vf610 +full:- +full:i2c
1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
8 #include <dt-bindings/clock/imx7ulp-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "imx7ulp-pinfunc.h"
15 interrupt-parent = <&intc>;
17 #address-cells = <1>;
18 #size-cells = <1>;
37 #address-cells = <1>;
38 #size-cells = <0>;
41 compatible = "arm,cortex-a7";
47 intc: interrupt-controller@40021000 {
48 compatible = "arm,cortex-a7-gic";
49 #interrupt-cells = <3>;
50 interrupt-controller;
55 rosc: clock-rosc {
56 compatible = "fixed-clock";
57 clock-frequency = <32768>;
58 clock-output-names = "rosc";
59 #clock-cells = <0>;
62 sosc: clock-sosc {
63 compatible = "fixed-clock";
64 clock-frequency = <24000000>;
65 clock-output-names = "sosc";
66 #clock-cells = <0>;
69 sirc: clock-sirc {
70 compatible = "fixed-clock";
71 clock-frequency = <16000000>;
72 clock-output-names = "sirc";
73 #clock-cells = <0>;
76 firc: clock-firc {
77 compatible = "fixed-clock";
78 clock-frequency = <48000000>;
79 clock-output-names = "firc";
80 #clock-cells = <0>;
83 upll: clock-upll {
84 compatible = "fixed-clock";
85 clock-frequency = <480000000>;
86 clock-output-names = "upll";
87 #clock-cells = <0>;
91 compatible = "simple-bus";
92 #address-cells = <1>;
93 #size-cells = <1>;
97 edma1: dma-controller@40080000 {
98 #dma-cells = <2>;
99 compatible = "fsl,imx7ulp-edma";
102 dma-channels = <32>;
120 clock-names = "dma", "dmamux0";
126 compatible = "fsl,sec-v4.0";
127 #address-cells = <1>;
128 #size-cells = <1>;
133 clock-names = "aclk", "ipg";
136 compatible = "fsl,sec-v4.0-job-ring";
142 compatible = "fsl,sec-v4.0-job-ring";
149 compatible = "fsl,imx7ulp-lpuart";
153 clock-names = "ipg";
154 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
155 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
156 assigned-clock-rates = <24000000>;
161 compatible = "fsl,imx7ulp-lpuart";
165 clock-names = "ipg";
166 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
167 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
168 assigned-clock-rates = <48000000>;
173 compatible = "fsl,imx7ulp-pwm";
175 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
176 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
178 #pwm-cells = <3>;
183 compatible = "fsl,imx7ulp-tpm";
188 clock-names = "ipg", "per";
192 compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
198 ahb-burst-config = <0x0>;
199 tx-burst-size-dword = <0x8>;
200 rx-burst-size-dword = <0x8>;
205 compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc";
206 #index-cells = <1>;
210 usbphy1: usb-phy@40350000 {
211 compatible = "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy";
215 #phy-cells = <0>;
219 compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
225 clock-names = "ipg", "ahb", "per";
226 bus-width = <4>;
227 fsl,tuning-start-tap = <20>;
228 fsl,tuning-step = <2>;
233 compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
239 clock-names = "ipg", "ahb", "per";
240 bus-width = <4>;
241 fsl,tuning-start-tap = <20>;
242 fsl,tuning-step = <2>;
246 scg1: clock-controller@403e0000 {
247 compatible = "fsl,imx7ulp-scg1";
251 clock-names = "rosc", "sosc", "sirc",
253 #clock-cells = <1>;
257 compatible = "fsl,imx7ulp-wdt";
261 assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
262 assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
263 timeout-sec = <40>;
266 pcc2: clock-controller@403f0000 {
267 compatible = "fsl,imx7ulp-pcc2";
269 #clock-cells = <1>;
281 clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
285 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
286 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
289 smc1: clock-controller@40410000 {
290 compatible = "fsl,imx7ulp-smc1";
292 #clock-cells = <1>;
295 clock-names = "divcore", "hsrun_divcore";
298 pcc3: clock-controller@40b30000 {
299 compatible = "fsl,imx7ulp-pcc3";
301 #clock-cells = <1>;
313 clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
321 compatible = "simple-bus";
322 #address-cells = <1>;
323 #size-cells = <1>;
327 lpi2c6: i2c@40a40000 {
328 compatible = "fsl,imx7ulp-lpi2c";
332 clock-names = "ipg";
333 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
334 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
335 assigned-clock-rates = <48000000>;
339 lpi2c7: i2c@40a50000 {
340 compatible = "fsl,imx7ulp-lpi2c";
344 clock-names = "ipg";
345 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
346 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
347 assigned-clock-rates = <48000000>;
352 compatible = "fsl,imx7ulp-lpuart";
356 clock-names = "ipg";
357 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
358 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
359 assigned-clock-rates = <48000000>;
364 compatible = "fsl,imx7ulp-lpuart";
368 clock-names = "ipg";
369 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
370 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
371 assigned-clock-rates = <48000000>;
375 memory-controller@40ab0000 {
376 compatible = "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc";
382 compatible = "fsl,imx7ulp-iomuxc1";
387 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
389 gpio-controller;
390 #gpio-cells = <2>;
392 interrupt-controller;
393 #interrupt-cells = <2>;
396 clock-names = "gpio", "port";
397 gpio-ranges = <&iomuxc1 0 0 20>;
401 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
403 gpio-controller;
404 #gpio-cells = <2>;
406 interrupt-controller;
407 #interrupt-cells = <2>;
410 clock-names = "gpio", "port";
411 gpio-ranges = <&iomuxc1 0 32 12>;
415 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
417 gpio-controller;
418 #gpio-cells = <2>;
420 interrupt-controller;
421 #interrupt-cells = <2>;
424 clock-names = "gpio", "port";
425 gpio-ranges = <&iomuxc1 0 64 16>;
429 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
431 gpio-controller;
432 #gpio-cells = <2>;
434 interrupt-controller;
435 #interrupt-cells = <2>;
438 clock-names = "gpio", "port";
439 gpio-ranges = <&iomuxc1 0 96 20>;
444 compatible = "simple-bus";
445 #address-cells = <1>;
446 #size-cells = <1>;
451 compatible = "fsl,imx7ulp-sim", "syscon";
456 compatible = "fsl,imx7ulp-ocotp", "syscon";