Lines Matching full:assigned

154 			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
155 			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
156 			assigned-clock-rates = <24000000>;
166 			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
167 			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
168 			assigned-clock-rates = <48000000>;
175 			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
176 			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
261 			assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
262 			assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
285 			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
286 			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
333 			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
334 			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
335 			assigned-clock-rates = <48000000>;
345 			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
346 			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
347 			assigned-clock-rates = <48000000>;
357 			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
358 			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
359 			assigned-clock-rates = <48000000>;
369 			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
370 			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
371 			assigned-clock-rates = <48000000>;